Method for specification and integration of reusable IP constraints
First Claim
Patent Images
1. A hardware-block timing-constraint specification method, for use at or below an RTL abstraction level, comprising:
- defining a plurality of hardware-block timing-constraint categories according to at least one of;
type of timing constraint; and
timing-constraint operating mode;
defining a plurality of hardware-block timing-constraint commands;
wherein each of the plurality of hardware-block timing-constraint commands is categorized into one of the plurality of hardware-block timing-constraint categories; and
encapsulating the plurality of hardware-block timing-constraint commands within a plurality of modules usable, via an application programming interface, in a standalone mode or an integrated mode.
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Abstract
A hardware-block constraint specification method includes defining a plurality of hardware-block constraint categories according to at least one of type of constraint and constraint operating mode and defining a plurality of hardware-block constraint commands. Each of the plurality of hardware-block constraint commands is categorized into one of the plurality of hardware-block constraint categories. The method also includes encapsulating the plurality of hardware-block constraint commands within a plurality of modules usable, via an application programming interface, in a stand-alone mode or an integrated mode.
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Citations
34 Claims
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1. A hardware-block timing-constraint specification method, for use at or below an RTL abstraction level, comprising:
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defining a plurality of hardware-block timing-constraint categories according to at least one of; type of timing constraint; and timing-constraint operating mode; defining a plurality of hardware-block timing-constraint commands; wherein each of the plurality of hardware-block timing-constraint commands is categorized into one of the plurality of hardware-block timing-constraint categories; and encapsulating the plurality of hardware-block timing-constraint commands within a plurality of modules usable, via an application programming interface, in a standalone mode or an integrated mode. - View Dependent Claims (2, 3, 4, 5, 6)
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7. An integrated-circuit synthesis method for use at or below an RTL abstraction level, comprising:
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integrating, via an application programming interface, a plurality of hardware-block timing-constraint modules into an electronic-design-automation environment; wherein at least one of the plurality of hardware-block timing-constraint modules is usable in a stand-alone mode or an integrated mode; and performing a timing analysis using the at least one of the plurality of hardware-block timing-constraint modules. - View Dependent Claims (8, 9)
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10. An article of manufacture for hardware-block timing-constraint specification for use at or below an RTL abstraction level, the article of manufacture comprising:
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at least one computer readable medium; processor instructions contained on the at least one computer readable medium, the processor instructions configured to be readable from the at least one computer readable medium by at least one processor and cause the at least one processor to operate as to facilitate; definition of a plurality of hardware-block timing-constraint categories according to at least one of; type of timing constraint; and timing-constraint operating mode; definition of a plurality of hardware-block timing-constraint commands; wherein each of the plurality of hardware-block timing-constraint commands is categorized into one of the plurality of hardware-block timing-constraint categories; encapsulation of the plurality of hardware-block timing-constraint commands within a plurality of modules usable, via an application programming interface, in a stand-alone mode or an integrated mode. - View Dependent Claims (11, 12, 13, 14, 15)
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16. A hardware-block synthesis-constraint specification method for use at or below an RTL abstraction level, comprising:
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defining a plurality of hardware-block synthesis-constraint categories, the hardware-block synthesis-constraint categories being defined according to at least one of; type of constraint; and constraint operating mode; defining a plurality of hardware-block synthesis-constraint commands; wherein each of the plurality of hardware-block synthesis-constraint commands is categorized into one of the plurality of hardware-block synthesis-constraint categories; encapsulating the plurality of hardware-block synthesis-constraint commands within a plurality of modules usable, via an application programming interface, in a stand-alone mode or an integrated mode. - View Dependent Claims (17, 18, 19)
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20. An article of manufacture for integrated-circuit timing analysis for use at or below an RTL abstraction level, the article of manufacture comprising:
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at least one computer readable medium; processor instructions contained on the at least one computer readable medium, the processor instructions configured to be readable from the at least one computer readable medium by at least one processor and thereby cause the at least one processor to operate as to facilitate; integration, via an application programming interface, of a plurality of hardware-block timing-constraint modules into an electronic-design-automation environment; wherein at least one of the plurality of hardware-block timing constraint modules is usable in a stand-alone mode or an integrated mode; and performance of a timing analysis using the at least one of the plurality of hardware-block timing-constraint modules. - View Dependent Claims (21, 22)
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23. An integrated-circuit synthesis method for use at or below an RTL abstraction level, comprising:
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integrating, via an application programming interface, a plurality of hardware-block synthesis-constraint modules into an electronic-design-automation environment; wherein at least one of the plurality of hardware-block synthesis-constraint modules is usable in a stand-alone mode or an integrated mode; and performing a synthesis using the at least one of the plurality of hardware block synthesis-constraint modules. - View Dependent Claims (24, 25)
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26. An article of manufacture for integrated-circuit synthesis for use at or below an RTL abstraction level, the article of manufacture comprising:
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at least one computer readable medium; processor instructions contained on the at least one computer readable medium, the processor instructions configured to be readable from the at least one computer readable medium by at least one processor and thereby cause the at least one processor to operate as to facilitate; integration, via an application programming interface, of a plurality of hardware-block synthesis-constraint modules into an electronic-design-automation environment; wherein at least one of the plurality of hardware-block synthesis constraint modules is usable in a stand-alone mode or an integrated mode; and performance of a synthesis using the at least one of the plurality of hardware-block synthesis-constraint modules. - View Dependent Claims (27, 28)
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29. An article of manufacture for hardware-block synthesis-constraint specification for use at or below an RTL abstraction level, the article of manufacture comprising:
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at least one computer readable medium; processor instructions contained on the at least one computer readable medium, the processor instructions configured to be readable from the at least one computer readable medium by at least one processor and cause the at least one processor to operate as to facilitate; definition of a plurality of hardware-block synthesis-constraint categories, the hardware-block synthesis-constraint categories being defined according to at least one of; type of constraint; and constraint operating mode; definition of a plurality of hardware-block synthesis-constraint commands; wherein each of the plurality of hardware-block synthesis-constraint commands is categorized into one of the plurality of hardware-block synthesis-constraint categories; and encapsulation of the plurality of hardware-block synthesis constraint commands within a plurality of modules usable, via an application programming interface, in a stand-alone mode or an integrated mode. - View Dependent Claims (30, 31, 32)
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33. A hardware-block constraint-specification method for use at or below an RTL abstraction level, comprising:
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defining a plurality of hardware-block constraint categories according to at least one of; type of constraint; and constraint operating mode; defining a plurality of hardware-block constraint commands; wherein each of the plurality of hardware-block constraint commands is categorized into one of the plurality of hardware-block constraint categories; and encapsulating the plurality of hardware-block constraint commands within a plurality of modules usable, via an application programming interface, in a stand-alone mode or an integrated mode.
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34. An article of manufacture for hardware-block constraint specification for use at or below an RTL abstraction level, the article of manufacture comprising:
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at least one computer readable medium; processor instructions contained on the at least one computer readable medium, the processor instructions configured to be readable from the at least one computer readable medium by at least one processor and cause the at least one processor to operate as to facilitate;
definition of a plurality of hardware-block constraint categories according to at least one of;type of constraint; and constraint operating mode; definition of a plurality of hardware-block constraint commands; wherein each of the plurality of hardware-block constraint commands is categorized into one of the plurality of hardware-block constraint categories; encapsulation of the plurality of hardware-block constraint commands within a plurality of modules usable, via an application programming interface, in a stand-alone mode or an integrated mode.
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Specification