Non-planar surface structures and process for microelectromechanical systems

• US 7,527,996 B2
• Filed: 04/19/2006
• Issued: 05/05/2009
• Est. Priority Date: 04/19/2006
• Status: Expired due to Fees

• Current Assignee: Snaptrack Incorporated (Qualcomm, Inc.)
• Original Assignee: Qualcomm MEMS Technologies Incorporated (Qualcomm, Inc.)
• Inventors: Akella, Sriram, Kogut, Lior, Luo, Qi
• Primary Examiner(s): Lindsay, Jr.; Walter L
• Assistant Examiner(s): MUSTAPHA, ABDULFATTAH B
• Application Number:
  US11/406,981
• Publication Number:
  US 20070249081A1
• Time in Patent Office: 1,112 Days
• Field of Search: 438/48, 438/50, 257/E29.001, 257/E29.028, 257/E29.052
• US Class Current: 438/48
• CPC Class Codes: B81B 3/0008 Structures for avoiding electrostatic attraction, e.g. avoiding charge accumulation
• CPC Class Codes: G02B 26/001 based on interference in an adjustable optical cavity interference filters G02B5/28; devices or arrangements using multiple reflections in spectrometry or monochromators G01J3/26

Abstract

Methods of making MEMS devices including interferometric modulators involve depositing various layers, including stationary layers, movable layers and sacrificial layers, on a substrate. Voids are formed in one or more of the various layers so as to form a non-planar surface on the movable and/or the stationary layers. The voids are formed to extend through less than the entire thickness of the layer where they are being formed. Other layers may be formed over the formed voids. Removal of the sacrificial layer from between the resulting non-planar movable and/or stationary layers results in a released MEMS device having reduced contact area between the movable and stationary layers when the MEMS device is actuated. The reduced contact area results in lower adhesion forces and reduced stiction during actuation of the MEMS device. These methods may be used to manufacture released and unreleased interferometric modulators.

Claims

1. A method of making a microelectromechanical system (MEMS) device, comprising:

providing a substrate;

forming a sacrificial layer over the substrate;

partially removing a portion of the sacrificial layer so as to form at least one void that extends through less than the entire thickness of the sacrificial layer, wherein the at least one void has a depth dimension in a range of about 100 angstroms to about 500 angstroms as measured perpendicular to the substrate;

forming an electrically conductive layer over at least a portion of the sacrificial layer and the at least one formed void, thereby forming a non-planar interface between the electrically conductive layer and the sacrificial layer; and

removing the sacrificial layer to form a cavity between the substrate and the electrically conductive layer.

2. The method of claim 1, wherein the substrate comprises a second electrically conductive layer.

3. The method of claim 2, wherein the second electrically conductive layer comprises indium tin oxide.

4. The method of claim 1, wherein the electrically conductive layer comprises a movable layer.

5. The method of claim 1, wherein the substrate comprises a partially reflective layer.

6. The method of claim 1, wherein partially removing the portion of the sacrificial layer comprises exposing the sacrificial layer to an etchant for a period of time effective to form the void.

7. The method of claim 1, further comprising patterning the sacrificial layer.

8. The method of claim 7, wherein the patterning comprises at least one of electron beam lithography and image transfer.

9. The method of claim 7, further comprising:

forming a support structure aperture in the sacrificial layer; and

depositing a support structure into the support structure aperture, the support structure configured to support the electrically conductive layer.

10. The method of claim 1, wherein partially removing the portion of the sacrificial layer further comprises:

patterning the sacrificial layer; and

etching the sacrificial layer.

11. A method of making an interferometric modulator, comprising:

providing a substrate;

forming a first electrically conductive layer over at least a portion of the substrate;

forming a first dielectric layer over at least a portion of the first electrically conductive layer;

partially removing a portion of a lower layer, wherein the lower layer comprises one of the first dielectric layer, and a layer between the first dielectric layer and the substrate so as to form at least one void that extends through less than the entire thickness of the lower layer in which the void is formed;

forming a sacrificial layer over at least a portion of the first dielectric layer and the at least one formed void;

forming a second electrically conductive layer over the sacrificial layer; and

selectively removing the sacrificial material against the first dielectric layer.

12. The method of claim 11, further comprising:

forming a second dielectric layer over at least a portion of the first dielectric layer containing the at least one void; and

forming the sacrificial material over the second dielectric layer.

13. The method of claim 11, further comprising planarizing the sacrificial layer prior to forming the second electrically conductive layer.

14. The method of claim 13, wherein planarizing comprises at least one of chemical mechanical polishing and spin coating.

15. The method of claim 11, wherein the at least one void is configured so as to form a raised portion having a cross sectional dimension in a range of about 2 micrometers to about 5 micrometers as measured parallel to the substrate.

16. The method of claim 11, wherein the at least one void is configured so as to form at least two raised portions in the first dielectric layer, wherein the at least two raised portions are separated by a distance in a range from about 4 micrometers to about 100 micrometers.

17. The method of claim 11, wherein the at least one void has a depth dimension in a range of about 100 angstroms to about 500 angstroms as measured perpendicular to the substrate.

18. The method of claim 11, wherein partially removing the portion of the lower layer comprises exposing the lower layer to an etchant for a period of time effective to form the void.

19. A method of making a microelectromechanical system (MEMS) device, comprising:

providing a substrate;

forming a sacrificial layer over the substrate;

patterning the sacrificial layer;

partially removing a portion of the patterned sacrificial layer by etching so as to form at least one void that extends through less than the entire thickness of the sacrificial layer;

forming an electrically conductive layer over at least a portion of the sacrificial layer and the at least one formed void, thereby forming a non-planar interface between the electrically conductive layer and the sacrificial layer; and

removing the sacrificial layer to form a cavity between the substrate and the electrically conductive layer.

20. The method of claim 19, wherein the at least one void has a depth dimension in a range of about 100 angstroms to about 500 angstroms as measured perpendicular to the substrate.