Method of manufacturing complementary diodes

• US 7,528,017 B2
• Filed: 09/15/2006
• Issued: 05/05/2009
• Est. Priority Date: 12/07/2005
• Status: Active Grant

• Current Assignee: Ensurge Micropower ASA
• Original Assignee: Kovio Incorporated (Ensurge Micropower ASA)
• Inventors: Smith, Patrick, Subramanian, Vivek
• Primary Examiner(s): Pham; Thanh V
• Application Number:
  US11/521,924
• Publication Number:
  US 20070128760A1
• Time in Patent Office: 963 Days
• Field of Search: 438/91, 438/141, 438/237, 438/328, 257/121, 257/E29.195
• US Class Current: 438/141
• CPC Class Codes: H01L 27/1285 using control of the annealing or irradiation parameters, e.g. using different scanning direction or intensity for different transistors
• CPC Class Codes: H01L 27/1288 employing particular masking sequences or specially adapted masks, e.g. half-tone mask
• CPC Class Codes: H01L 27/1292 using liquid deposition, e.g. printing
• CPC Class Codes: H01L 29/86 controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
• CPC Class Codes: Y10S 257/91 Diode arrays, e.g. diode read-only memory array

Abstract

Process variation-tolerant diodes and diode-connected thin film transistors (TFTs), printed or patterned structures (e.g., circuitry) containing such diodes and TFTs, methods of making the same, and applications of the same for identification tags and sensors are disclosed. A patterned structure comprising a complementary pair of diodes or diode-connected TFTs in series can stabilize the threshold voltage (V_t) of a diode manufactured using printing or laser writing techniques. The present invention advantageously utilizes the separation between the V_t of an NMOS TFT (V_tn) and the V_t of a PMOS TFT (V_tp) to establish and/or improve stability of a forward voltage drop across a printed or laser-written diode. Further applications of the present invention relate to reference voltage generators, voltage clamp circuits, methods of controlling voltages on related or differential signal transmission lines, and RFID and EAS tags and sensors.

Claims

1. A method of making complementary diodes, comprising:

a) forming a first patterned semiconductor layer on a substrate, the first patterned semiconductor layer having a first conductivity type;

b) forming a second patterned semiconductor layer on the substrate, the second patterned semiconductor layer having a second conductivity type;

c) forming a first patterned gate structure on the first patterned semiconductor layer and a second patterned gate structure on the second patterned semiconductor layer,

d) forming a patterned insulator layer over the first and second patterned semiconductor layers, the first and second patterned gate structures, and the substrate; and

e) forming a first patterned metal layer on the patterned insulator layer, electrically connecting the first and second patterned semiconductor layers with the first and second patterned gate structures.

2. The method of claim 1, wherein forming the first patterned semiconductor layer comprises printing or laser writing a first semiconductor composition, and forming the second patterned semiconductor layer comprises printing or laser writing a second semiconductor composition.

3. The method of claim 2, wherein at least one of the first and second semiconductor compositions comprises an ink containing a silane and/or silicon nanoparticles.

4. The method of claim 1, wherein forming the first and second patterned semiconductor layers comprises printing one or more semiconductor ink compositions containing a silane and/or silicon nanoparticles.

5. The method of claim 1, wherein forming the first patterned metal layer comprises printing a first metal composition.

6. The method of claim 1, wherein the patterned gate structures comprise a second patterned metal layer on a patterned gate dielectric layer.

7. The method of claim 1, wherein forming the patterned gate structures comprises printing or laser writing a second metal composition on a gate dielectric layer.

8. The method of claim 1, wherein said first patterned gate structure comprises a semiconductor layer having a first conductivity type on a first gate dielectric layer, and said second patterned gate structure comprises a semiconductor layer having a second conductivity type on a second gate dielectric layer.

9. The method of claim 1, wherein forming said first and second patterned gate structures comprises the steps of:

a) forming a gate dielectric layer on said first and second patterned semiconductor layers;

b) forming a gate electrode layer on the gate dielectric layer; and

c) selectively removing portions of the gate electrode layer and the gate dielectric layer.

10. The method of claim 9, wherein forming the gate electrode layer comprises printing a semiconductor ink composition containing a silane and/or silicon nanoparticles on the gate dielectric layer.

11. The method of claim 1, wherein forming said first and second patterned gate structures comprises the steps of:

a) forming a gate dielectric layer on said first and second patterned semiconductor layers;

b) forming first and second patterned gate electrode layers; and

c) selectively removing exposed portions of the gate dielectric layer.

12. The method of claim 11, wherein said first and second patterned gate electrode layers are formed substantially simultaneously.

13. The method of claim 11, wherein forming the first patterned gate electrode layer comprises printing or laser writing a first semiconductor composition, and forming the second patterned semiconductor layer comprises printing or laser writing a second semiconductor composition.

14. The method of claim 13, wherein said first semiconductor composition has a first conductivity type and said second semiconductor composition has a second conductivity type.

15. The method of claim 1, further comprising forming heavily doped source and drain regions in each of the first and second patterned semiconductor layers after forming said first and second patterned gate structures.

16. The method of claim 15, wherein forming said heavily doped drain regions comprises:

a) selectively depositing a first spin-on-dopant layer containing a dopant of a first conductivity type on said first patterned semiconductor layer;

b) selectively depositing a second spin-on-dopant layer containing a dopant of a second conductivity type on said second patterned semiconductor layer; and

c) annealing said first and second spin-on-dopant layers to form said heavily doped drain regions.

17. The method of claim 16, wherein selectively depositing said first spin-on-dopant layer comprises printing said first spin-on-dopant layer in a pattern on said first patterned semiconductor layer, and selectively depositing said second spin-on-dopant layer comprises printing said second spin-on-dopant layer in a pattern on said second patterned semiconductor layer.

18. The method of claim 1, wherein said first patterned semiconductor layer and second patterned semiconductor layer are formed substantially simultaneously.

19. The method of claim 1, wherein said substrate comprises an insulator.

20. The method of claim 1, wherein said substrate comprises a conducting or semiconducting material with an insulator thereon.

21. The method of claim 20, wherein said substrate comprises a metal foil.

22. The method of claim 21, wherein said insulator comprises an oxide of the metal of said metal foil.

23. The method of claim 11, wherein forming said gate dielectric layer comprises oxidizing a surface of said first and second patterned semiconductor layers.

24. The method of claim 1, wherein forming said patterned insulator layer comprises:

a) printing an insulator-containing composition in a pattern; and

b) annealing said insulator-containing composition to form the patterned insulator layer.

25. The method of claim 24, wherein said insulator-containing composition comprises a glass.

26. The method of claim 1, wherein forming said patterned insulator layer comprises:

a) depositing an insulator-containing composition;

b) annealing said insulator-containing composition to form an insulator layer; and

c) forming holes in the insulator layer to form the patterned insulator layer.

27. The method of claim 26, wherein said insulator-containing composition comprises a glass.