Nonplanar transistors with metal gate electrodes

• US 7,528,025 B2
• Filed: 11/21/2007
• Issued: 05/05/2009
• Est. Priority Date: 09/30/2004
• Status: Active Grant

• Current Assignee: Tahoe Research Limited (f/k/a Learndale Limited) (Vector Capital Corporation)
• Original Assignee: Intel Corporation
• Inventors: Dovle, Brian S., Kavalleros, Jack, Shah, Uday, Chau, Robert S., Brask, Justin K., Doczy, Mark
• Primary Examiner(s): Cao; Phat X
• Application Number:
  US11/986,510
• Publication Number:
  US 20080090397A1
• Time in Patent Office: 531 Days
• Field of Search: 438/183, 438/926
• US Class Current: 438/183
• CPC Class Codes: H01L 21/845 including field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/1211 combined with field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/0673 oriented parallel to a substrate
• CPC Class Codes: H01L 29/41791 for transistors with a horizontal current flow in a vertical sidewall, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/66439 with a one- or zero-dimensional channel, e.g. quantum wire FET, in-plane gate transistor [IPG], single electron transistor [SET], striped channel transistor, Coulomb blockade transistor with an active layer made of a group 13/15 material H01L29/66469
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: Y10S 438/926 Dummy metallization
• CPC Class Codes: Y10S 438/974 Substrate surface preparation

Abstract

A semiconductor device comprising a semiconductor body having a top surface and a first and second laterally opposite sidewalls as formed on an insulating substrate is claimed. A gate dielectric is formed on the top surface of the semiconductor body and on the first and second laterally opposite sidewalls of the semiconductor body. A gate electrode is then formed on the gate dielectric on the top surface of the semiconductor body and adjacent to the gate dielectric on the first and second laterally opposite sidewalls of the semiconductor body. The gate electrode comprises a metal film formed directly adjacent to the gate dielectric layer. A pair of source and drain regions are then formed in the semiconductor body on opposite sides of the gate electrode.

Claims

1. A method of forming a nonplanar device CMOS integrated circuit comprising:

forming an n type and a p type semiconductor bodies, each semiconductor body comprising a top surface and sidewalls;

forming a first sacrificial gate electrode over the top surface and sidewalls of the n type semiconductor body, wherein a portion of the n type semiconductor body area under the first sacrificial gate electrode defines an n type semiconductor channel region;

forming a second sacrificial gate electrode over the top surface and sidewalls of the p type semiconductor body, wherein a portion of the p type semiconductor body area under the first sacrificial gate electrode defines a p type semiconductor channel region;

forming a dielectric layer over said first and said second sacrificial gate electrodes;

planarizing said dielectric layer;

revealing the top surface of said first and second sacrificial gate electrodes;

removing said first sacrificial gate electrode to form a first opening over said n type channel region and removing said second sacrificial gate electrode to form a second opening over said p type semiconductor channel region;

forming a gate dielectric layer in said first opening on said n type semiconductor channel region and in said second opening on said p type semiconductor channel region;

forming a metal gate electrode material onto said gate dielectric layer in said first opening and onto said gate dielectric layer in second opening and above said planarized dielectric layer; and

polishing said gate electrode material from above said dielectric to form a first gate electrode over said gate dielectric layer in said opening and a second gate electrode on said gate dielectric layer in said second opening.

2. The method of claim 1 wherein said gate electrode material comprises a lower metal film and an upper metal film.

3. The method of claim 2 wherein said lower metal film comprises a midgap work function material.

4. The method of claim 3 wherein said upper film is selected from the group consisting of copper and tungsten.

5. The method of claim 1 further comprising after forming said first and second gate electrodes by polishing, removing said dielectric layer.

6. The method of claim 5 further comprising after removing said dielectric layer, blanket depositing a silicon nitride film on and around said first gate electrode and said second gate electrode.

7. The method of claim 6 further comprising forming a second dielectric layer over said silicon nitride film.