Vertical wrap-around-gate field-effect-transistor for high density, low voltage logic and memory array

• US 7,528,439 B2
• Filed: 05/23/2006
• Issued: 05/05/2009
• Est. Priority Date: 08/30/2004
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Tang, Sanh D., Srinivasan, Anand, Burke, Robert J.
• Primary Examiner(s): Ngo; Ngan
• Assistant Examiner(s): LIU, BENJAMIN T
• Application Number:
  US11/438,419
• Publication Number:
  US 20070048943A1
• Time in Patent Office: 1,078 Days
• Field of Search: 257/327, 257/328, 257/329, 257/401, 257/371, 257/E27.067, 257/E27.096, 257/E29.118, 257/E29.122, 257/E29.131, 257/E29.267, 257/E29.274
• US Class Current: 257/327
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 29/42392 fully surrounding the channel, e.g. gate-all-around
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence
• CPC Class Codes: H01L 29/78642 Vertical transistors
• CPC Class Codes: H10B 12/053 the transistor being at least partially in a trench in the substrate vertical transistor in combination with a capacitor formed in a substrate trench H10B12/0383
• CPC Class Codes: H10B 12/315 with the capacitor higher than a bit line
• CPC Class Codes: H10B 12/482 Bit lines
• CPC Class Codes: H10B 12/488 Word lines

Abstract

A vertical transistor having a wrap-around-gate and a method of fabricating such a transistor. The wrap-around-gate (WAG) vertical transistors are fabricated by a process in which source, drain and channel regions of the transistor are automatically defined and aligned by the fabrication process, without photolithographic patterning.

Claims

1. A semiconductor structure containing a vertical transistor, comprising:

a substrate, wherein at least a portion of the work surface of the substrate is formed of polysilicon;

a polysilicon pillar extending vertically from the polysilicon surface of the substrate, the pillar having a top end, a top portion, a central portion, and a bottom portion;

a first source/drain region defined in the top portion of the pillar;

a channel region defined in the central portion of the pillar;

a second source/drain region defined in the bottom portion of the pillar;

a dielectric layer surrounding the central portion of the pillar and being in alignment with the channel region of the transistor;

a transistor gate surrounding the central portion of the pillar with the dielectric layer between the transistor gate and the pillar, the transistor gate being aligned with the channel region of the transistor; and

a spacer layer formed around only the top portion of the pillar and the first source/drain region.

2. The structure according to claim 1, wherein the thickness of the transistor gate corresponds with the thickness of the spacer layer.

3. The structure according to claim 2, wherein the top end of the pillar has been silicided.

4. The structure according to claim 2, wherein the spacer layer comprises a nitride material.

5. The structure according to claim 1, further comprising a conductive path extending away from the transistor gate, wherein the conductive path and the transistor gate are formed of the same material, and the conductive path is formed as an extension of the transistor gate.

6. The structure according to claim 5, wherein the transistor gate and conductive path are formed of metal.

7. The structure according to claim 5, wherein the transistor gate and conductive path are formed of polysilicon.

8. The structure according to claim 7, wherein the conductive path in a silicided conductive path.

9. The structure according to claim 5, further comprising at least one conductive plug, each conductive plug respectively contacting one of the first source/drain region, the polysilicon portion of the substrate from which the pillar extends, and the conductive path extending from the transistor gate.