Methods for slow test time detection of an integrated circuit during parallel testing

• US 7,528,622 B2
• Filed: 12/28/2006
• Issued: 05/05/2009
• Est. Priority Date: 07/06/2005
• Status: Active Grant

• Current Assignee: Optimal Plus Ltd. (Emerson Electric Company)
• Original Assignee: Optimal Test Limited
• Inventors: Golan, Avi, Linde, Reed, Balog, Gil
• Primary Examiner(s): PATEL, PARESH H
• Application Number:
  US11/646,588
• Publication Number:
  US 20070132477A1
• Time in Patent Office: 859 Days
• Field of Search: None
• US Class Current: 324/762.02
• CPC Class Codes: G01R 31/2601 Apparatus or methods therefor G01R31/2607, G01R31/2642 take precedence
• CPC Class Codes: G01R 31/2894 Aspects of quality control [QC] G01R31/31718 takes precedence; program control for QC G05B19/41875
• CPC Class Codes: G01R 31/31707 Test strategies methods for generation of test sequences G01R31/318371
• CPC Class Codes: G01R 31/3172 Optimisation aspects, e.g. using functional pin as test pin, pin multiplexing
• CPC Class Codes: G01R 31/318511 Wafer Test

Abstract

Methods and systems for semiconductor testing are disclosed. In one embodiment, devices which are testing too slowly are prevented from completing testing, thereby allowing untested devices to begin testing sooner.

Claims

1. A method of testing semiconductor devices comprising:

while a test program is being applied to a semiconductor device in parallel with at least one other semiconductor device, recognizing said semiconductor device as a candidate for test aborting because said device is testing too slowly compared to at least one other device being tested in parallel;

deciding whether to abort testing on said candidate; and

preventing said candidate from completing said test program, if said decision is to abort;

wherein after said device has completed said test program or has been prevented from completing said test program and if there is at least one remaining untested semiconductor device, said test program is applied to at least one of said remaining untested semiconductor devices.

2. The method of claim 1, wherein said recognizing includes:

after another device in a parallel testing group including said semiconductor device has completed said test program, recognizing at that point that said device is a candidate for test aborting because an anticipated test time for said device to complete said test program is too long.

3. The method of claim 2, wherein said anticipated test time is too long because a summation of typical test times for all at least one remaining test in said test program exceeds a difference between a maximum test time for said test program and a typical test time for said test program.

4. The method of claim 2, wherein said recognizing at that point that said device is a candidate for test aborting includes:

looking up in a table an entry for a test which is currently being applied to said device; and

based on said entry recognizing that at that point said device as a candidate for test aborting.

5. The method of claim 1, wherein said test program is applied to at least one of said remaining untested semiconductor devices only after each device in a parallel testing group including said semiconductor device has completed said test program or has been prevented from completing said test program.

6. The method of claim 1, wherein said test program is applied to at least one of said remaining untested semiconductor devices by redeploying a test site being used to test said device to an untested semiconductor device within a same touchdown after said device has completed said test program or has been prevented from completing said test program.

7. The method of claim 1, wherein said preventing said candidate from completing said test program includes aborting testing on said device prior to a last device in a parallel testing group including said device completes said test program.

8. The method of claim 1, wherein at least one device in a parallel testing group including said device fails at least one test, causing said at least one device to be prevented from completing said test program, or wherein at least one device in said parallel group including said device has testing aborted because of testing too slowly and is therefore prevented from completing said test program.

9. The method of claim 1, wherein said decision is to abort and wherein said device is discarded.

10. The method of claim 1, wherein said decision is to abort and wherein said device is retested at a later time.

11. The method of claim 1, wherein said deciding includes:

recognizing that said device is a candidate for test aborting based on a customized value for a test time parameter.

12. The method of claim 1, wherein said deciding whether to abort is based at least partially on a yield criterion.

13. The method of claim 1, wherein said deciding includes:

deciding that said candidate should have testing aborted, as a corollary of being a candidate.

14. A computer program product comprising a computer useable medium having computer readable program code embodied therein for testing semoconductor devices, the computer program product comprising:

computer readable program code for causing the computer, while a test program is being applied to a semiconductor device in parallel with at least one other semiconductor device, to recognize said semiconductor device as a candidate for test aborting because said device is testing too slowly compared to at least one other device being tested in parallel;

computer readable program code for causing the computer to decide whether to abort testing on said candidate; and

computer readable program code for causing the computer to prevent said candidate from completing said test program, if said decision is to abort;

wherein after said device has completed said test program or has been prevented from completing said test program and if there is at least one remaining untested semiconductor device, said test program is applied to at least one of said remaining untested semiconductor devices.