On die RFID tag antenna

• US 7,528,724 B2
• Filed: 02/28/2005
• Issued: 05/05/2009
• Est. Priority Date: 02/28/2005
• Status: Active Grant

• Current Assignee: Impinj, Inc.
• Original Assignee: Impinj, Inc.
• Inventors: Horch, Andrew E.
• Primary Examiner(s): Nguyen; Tai T
• Application Number:
  US11/069,005
• Publication Number:
  US 20060202831A1
• Time in Patent Office: 1,527 Days
• Field of Search: 340/572.8, 340/572.2, 340/572.4, 257/679, 257/787, 257/528, 257/678, 257/409, 257/452, 257/503, 235/492, 235/487, 235/488
• US Class Current: 340/572.2
• CPC Class Codes: G06K 19/07749 the record carrier being capable of non-contact communication, e.g. constructional details of the antenna of a non-contact smart card
• CPC Class Codes: G06K 7/0095 Testing the sensing arrangement, e.g. testing if a magnetic card reader, bar code reader, RFID interrogator or smart card reader functions properly testing of electrical circuits G01R31/28
• CPC Class Codes: H01L 23/5227 Inductive arrangements or effects of, or between, wiring layers other inductive arrangements H01L23/645
• CPC Class Codes: H01L 23/585 comprising conductive layers or plates or strips or rods or rings H01L23/60, H01L23/62, H01L23/64, H01L23/66 take precedence
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/3011 Impedance

Abstract

Wirelessly testing an RFID tag before it is packaged or otherwise entered into a process reserved for “working” RFID tags is described. Various processes that employ such wireless testing as well as various “on-die” RFID tag antennae designs for facilitating the wireless testing are also described.

Claims

1. A semiconductor chip, comprising:

a) an active device area comprising transistors;

b) a die seal ring substantially surrounding said active device area;

c) a substrate beneath said active device area and die seal ring;

d) an on-die antenna having wiring that;

i) resides outside said active device area and die seal ring;

ii) winds around said active device area and die seal ring;

iii) is electrically isolated from said die seal ring; and

,

e) a conductive path that runs from said on-die antenna to said active device area, wherein, at least a portion of said conductive path is embedded within said substrate, said conductive path being electrically coupled to;

i) said wiring, and,

ii) metal within said active device area;

and wherein said embedded portion of said conductive path comprises an N doped well.

2. The semiconductor chip of claim 1 wherein said embedded portion of said conductive path comprises an N type source/drain region.

3. The semiconductor chip of claim 1 wherein a PN junction exists between said embedded portion of said conductive path and said substrate'"'"'s bulk material.

4. The semiconductor chip of claim 3 wherein a pair of PN junctions exist between said embedded portion of said conductive path and said substrate'"'"'s bulk material.

5. The semiconductor chip of claim 1 wherein said on-die antenna is comprised of a stacked structure comprising a bar via, a bar contact and a continuous wire to thwart penetration of contaminants into said active device area.

6. The semiconductor chip of claim 1 wherein a length of said wiring does not make contact to a bar via or a bar contact.

7. The semiconductor chip of claim 1 wherein said wiring serpentines back and forth in a same plane outside an edge of said semiconductor chip'"'"'s active device area.

8. A semiconductor chip, comprising:

a) an active device area;

b) a die seal ring substantially surrounding said active device area;

c) a substrate beneath said active device area and said die seal ring;

d) an antenna outside said die seal ring, said antenna electrically isolated from said die seal ring; and

,

e) a conductive path coupled to said antenna and wiring within said active device area, said conductive path electrically isolated from said die seal ring, wherein, said conductive path is embedded within said substrate beneath said die seal ring and wherein said conductive path comprises an N region.

9. The semiconductor chip of claim 8 wherein said semiconductor chip is part of an RFID tag.

10. The semiconductor chip of claim 8 wherein said conductive path comprises an N well.

11. The semiconductor chip of claim 8 wherein said conductive path comprises an N source/drain region.

12. A semiconductor chip, comprising:

a) an active device area comprising transistors;

b) a die seal ring substantially surrounding said active device area;

c) a substrate beneath said die seal ring and said active device area;

d) an on-die antenna having wiring that;

i) resides outside said active device area and said die seal ring;

ii) winds around said active device area and said die seal ring;

iii) is electrically isolated from said die seal ring; and

,

e) a conductive path that runs from said on-die antenna to said active device area, wherein, at least a portion of said conductive path is embedded within said substrate, said conductive path being electrically coupled to;

i) said wiring, and,

ii) metal within said active device area; and

wherein said embedded portion of said conductive path comprises a P doped well.

13. The semiconductor chip of claim 12 wherein said embedded portion of said conductive path comprises a P source/drain region.

14. The semiconductor chip of claim 12 wherein a PN junction exists between said embedded portion of said conductive path and said substrate'"'"'s bulk material.

15. The semiconductor chip of claim 14 wherein a pair of PN junctions exist between said embedded portion of said conductive path and said substrate'"'"'s bulk material.

16. The semiconductor chip of claim 12 wherein said on-die antenna is comprised of a stacked structure comprising a bar via, a bar contact and a continuous wire to thwart penetration of contaminants into said active device area.

17. The semiconductor chip of claim 12 wherein a length of said wiring does not make contact to a bar via or a bar contact.

18. The semiconductor chip of claim 12 wherein said wiring serpentines back and forth in a same plane outside an edge of said semiconductor chip'"'"'s active device area.

19. A semiconductor chip, comprising:

a) an active device area;

b) a die seal ring substantially surrounding said active device area;

c) a substrate beneath said active device area and die seal ring;

d) an antenna outside said die seal ring, said antenna electrically isolated from said die seal ring; and

,

e) a conductive path coupled to said antenna and wiring within said active device area, said conductive path electrically isolated from said die seal ring, wherein, said conductive path is embedded within said substrate beneath said die seal ring and wherein said conductive path comprises a P region.

20. The semiconductor chip of claim 19 wherein said semiconductor chip is part of an RFID tag.

21. The semiconductor chip of claim 19 wherein said conductive path comprises a P source/drain region.

22. The semiconductor chip of claim 19 wherein said conductive path comprises a P well.