Analog-to-digital converter system with increased sampling frequency

• US 7,528,756 B2
• Filed: 03/22/2007
• Issued: 05/05/2009
• Est. Priority Date: 03/22/2007
• Status: Expired due to Fees

• Current Assignee: Array Portfolio LLC
• Original Assignee: VNS Portfolio LLC
• Inventors: Moore, Charles H., Snively, Leslie O., Huie, John
• Primary Examiner(s): JEANGLAUDE, JEAN BRUNER
• Application Number:
  US11/726,739
• Publication Number:
  US 20080231489A1
• Time in Patent Office: 775 Days
• Field of Search: 341/155, 341/156, 370/286, 370/352
• US Class Current: 341/155
• CPC Class Codes: H03M 1/1215 using time-division multiplexing
• CPC Class Codes: H03M 1/1245 Details of sampling arrangements or methods

Abstract

An improvement in sampling a high frequency input analog signal and converting it to a digital output signal is accomplished by using a multitude of analog-to-digital converters in conjunction with a distributed sampling system. This combination of multiple converters and a distributed sampling system allows use of conventional device processing, such as that of 0.18 micron silicon, and also provides accurate sampling of very high frequency input signals. The distributed sampling system provides multiple samplings of the input signal by using a different ADC for each sampling, wherein each sampling is sequentially offset a certain amount of time from the most recent preceding sampling. The samplings from the multitude of ADCs are combined to form a single contiguous digital output signal. Types of distributed sampling systems include a multitude of elongated trace patterns interconnected in series, a specified permittivity material device, and a sequencer or multiplier.

Claims

1. A method of sampling an analog signal, comprising:

providing an input analog signal;

routing a timing signal through a distributed sampling system;

sampling said input analog signal a plurality of times using a plurality of analog-to-digital converters (ADCs), respectively; and

combining each of said plurality of input analog signal samplings to form a single contiguous digital output signal, wherein;

said distributed sampling system provides a plurality of sequential sampling prompts.

2. The method of claim 1, further comprising:

providing a plurality of central processing units (CPUs) connected to said plurality of ADCs, respectively.

3. The method of claim 2, wherein:

some of said plurality of CPUs are dedicated to their respective connected ADCs.

4. The method of claim 2, wherein:

some of said plurality of CPUs are general purpose CPUs.

5. The method of claim 1, wherein:

said plurality of sequential sampling prompts causes each of said samplings to occur after an amount of time from a most recent preceding sampling.

6. The method of claim 1, wherein:

each of said plurality of sequential sampling prompts causes each of said samplings to occur in sequence.

7. The method of claim 1, wherein:

each of said plurality of sequential sampling prompts corresponds respectively to each of said samplings.

8. The method of claim 1, wherein:

said combining of samplings supports a Fourier Transformation function.

9. The method of claim 1, wherein:

each of said plurality of ADCs is capable of sampling at a pre-determined sampling rate; and

said method is equivalent to using a single ADC which is capable of sampling at a rate of said pre-determined sampling rate multiplied by a total number of ADCs used.

10. An analog-to-digital converter (ADC) sampling system, comprising:

a plurality of analog-to-digital converters (ADCs); and

a distributed sampling system, comprising;

a plurality of distribution stations which are connected together in series to form a junction between each of said stations; and

a plurality of tap lines connected between each of said junctions and each of said plurality of ADCs, respectively.

11. The ADC system of claim 10, further comprising:

an input analog signal; and

a timing signal.

12. The ADC system of claim 10, further comprising:

a plurality of central processing units (CPUs) connected to said plurality of ADCs, respectively.

13. The ADC system of claim 12, wherein:

some of said plurality of CPUs are dedicated to their respective connected ADCs.

14. The ADC system of claim 12, wherein:

some of said plurality of CPUs are general purpose CPUs.

15. The ADC system of claim 10, wherein:

some of said plurality of ADCs comprise;

a differential op amp system.

16. The ADC system of claim 15, wherein:

said differential op amp system comprises;

two input sources;

an op amp; and

a voltage controlled oscillator (VCO).

17. The ADC system of claim 15, wherein:

said differential op amp system produces a common mode rejection ratio.

18. The ADC system of claim 15, wherein:

said differential op amp system provides a reduction of noise signals.

19. A method of sampling an analog signal using a distributed sampling system, comprising:

providing a plurality of conductive trace patterns which are connected together in series to form a junction between each of said patterns;

routing a timing signal through said plurality of conductive trace patterns;

providing a plurality of sequential sampling prompts at each of said junctions;

sampling an input analog signal using a plurality of analog-to-digital converters (ADCs); and

combining each of said input analog signal samplings to form a single contiguous digital output signal.

20. The method of claim 19, further comprising:

providing a plurality of central processing units (CPUs) connected to said plurality of ADCs, respectively.

21. The method of claim 20, wherein some of said plurality of CPUs are dedicated to their respective connected ADCs.

22. The method of claim 20, wherein some of said plurality of CPUs are general purpose CPUs.

23. The method of claim 19, wherein:

said plurality of sequential sampling prompts causes each of said samplings to occur after an amount of time from a most recent preceding sampling.

24. The method of claim 19, wherein:

each of said plurality of sequential sampling prompts causes each of said samplings to occur in sequence.

25. The method of claim 19, wherein:

each of said plurality of sequential sampling prompts corresponds respectively to each of said samplings.

26. The method of claim 19, wherein:

said combining of samplings supports a Fourier Transformation function.

27. The method of claim 19, wherein:

each of said plurality of ADCs is capable of sampling at a pre-determined sampling rate; and

said method is equivalent to using a single ADC which is capable of sampling at a rate of said pre-determined sampling rate multiplied by a total number of ADCs used.

28. A method of sampling an analog signal using a distributed sampling system, comprising:

providing a device comprised of a specific permittivity material;

routing a timing signal through said device;

providing a plurality of sequential sampling prompts at a plurality of equi-distant points along said device, respectively;

sampling an input analog signal using a plurality of analog-to-digital converters (ADCs); and

combining each of said input analog signal samplings to form a single contiguous digital output signal.

29. The method of claim 28, further comprising:

providing a plurality of central processing units (CPUs) connected to said plurality of ADCs, respectively.

30. The method of claim 29, wherein some of said plurality of CPUs are dedicated to their respective connected ADCs.

31. The method of claim 29, wherein some of said plurality of CPUs are general purpose CPUs.

32. The method of claim 28, wherein:

said plurality of sequential sampling prompts causes each of said samplings to occur after an amount of time from a most recent preceding sampling.

33. The method of claim 28, wherein:

each of said plurality of sequential sampling prompts causes each of said samplings to occur in sequence.

34. The method of claim 28, wherein:

each of said plurality of sequential sampling prompts corresponds respectively to each of said samplings.

35. The method of claim 28, wherein:

said combining of samplings supports a Fourier Transformation function.

36. The method of claim 28, wherein:

each of said plurality of ADCs is capable of sampling at a pre-determined sampling rate; and

said method is equivalent to using a single ADC which is capable of sampling at a rate of said pre-determined sampling rate multiplied by a total number of ADCs used.

37. A method of sampling an analog signal using a distributed sampling system, comprising:

providing a sequencer device comprised of a plurality of triggers, which are connected to a plurality of analog-to-digital converters (ADCs), respectively;

inputting a plurality of timing signal pulses into said plurality of triggers, respectively;

sampling an input analog signal a plurality of times using said plurality of ADCs, respectively; and

combining each of said samplings to form a single contiguous digital output signal.

38. The method of claim 37, further comprising:

providing a plurality of central processing units (CPUs) connected to said plurality of ADCs, respectively.

39. The method of claim 38, wherein some of said plurality of CPUs are dedicated to their respective connected ADCs.

40. The method of claim 38, wherein some of said plurality of CPUs are general purpose CPUs.

41. The method of claim 37, wherein:

said plurality of sequential sampling prompts causes each of said samplings to occur after an amount of time from a most recent preceding sampling.

42. The method of claim 37, wherein:

each of said plurality of sequential sampling prompts causes each of said samplings to occur in sequence.

43. The method of claim 37, wherein:

each of said plurality of sequential sampling prompts corresponds respectively to each of said samplings.

44. The method of claim 37, wherein:

said combining of samplings supports a Fourier Transformation function.

45. The method of claim 37, wherein:

each of said plurality of ADCs is capable of sampling at a pre-determined sampling rate; and

said method is equivalent to using a single ADC which is capable of sampling at a rate of said pre-determined sampling rate multiplied by a total number of ADCs used.

46. The method of claim 37, further comprising:

a clock generating block.

47. The method of claim 46, wherein:

said clock generating block comprises a ring oscillator.

48. A method of sampling an analog signal using a distributed sampling system, comprising:

providing a plurality of inverter pairs which are connected together in series to form a junction between each of said plurality of inverter pairs;

routing a timing signal through said plurality of inverter pairs;

providing a plurality of sequential sampling prompts at each of said junctions;

sampling an input analog signal using a plurality of analog-to-digital converters (ADCs); and

combining each of said input analog signal samplings to form a single contiguous digital output signal.

49. The method of claim 48, further comprising:

a plurality of central processing units (CPUs) connected to said plurality of ADCs, respectively.

50. The method of claim 49, wherein some of said plurality of CPUs are dedicated to their respective connected ADCs.

51. The method of claim 49, wherein some of said plurality of CPUs are general purpose CPUs.

52. The method of claim 48, wherein:

said plurality of sequential sampling prompts causes each of said samplings to occur after an amount of time from a most recent preceding sampling.

53. The method of claim 48, wherein:

each of said plurality of sequential sampling prompts causes each of said samplings to occur in sequence.

54. The method of claim 48, wherein:

each of said plurality of sequential sampling prompts corresponds respectively to each of said samplings.

55. The method of claim 48, wherein:

said combining of samplings supports a Fourier Transformation function.

56. The method of claim 48, wherein:

each of said plurality of ADCs is capable of sampling at a pre-determined sampling rate; and

said method is equivalent to using a single ADC which is capable of sampling at a rate of said pre-determined sampling rate multiplied by a total number of ADCs used.

57. A multiple core processor, comprising:

a plurality of interconnected central processing units (CPUs);

a plurality of analog-to-digital converters (ADCs) connected to said plurality of CPUs; and

a distributed sampling system, comprising;

a plurality of distribution stations which are connected together in series to form a junction between each of said stations; and

a plurality of tap lines connected between each of said junctions and each of said plurality of ADCs, respectively.

58. The processor of claim 57, wherein:

some of said plurality of CPUs are dedicated to their respective connected ADCs.

59. The processor of claim 57, wherein:

some of said plurality of CPUs are general purpose CPUs.

60. The processor of claim 57, wherein:

some of said plurality of ADCs comprise a differential op amp system.

61. The processor of claim 57, wherein:

an output of said processor comprises an accumulation of sequential input analog signal samplings.

62. The processor of claim 61, wherein:

said output comprises a digital output signal.