Variable pixel clock electronic shutter control

• US 7,528,873 B2
• Filed: 12/28/2005
• Issued: 05/05/2009
• Est. Priority Date: 07/20/2001
• Status: Active Grant

• Current Assignee: Aptina Imaging Corporation (ON Semiconductor Corporation)
• Original Assignee: Aptina Imaging Corporation (ON Semiconductor Corporation)
• Inventors: Van Blerkom, Daniel
• Primary Examiner(s): Vu; Ngoc-Yen T
• Assistant Examiner(s): Giles; Nicholas G
• Application Number:
  US11/318,512
• Publication Number:
  US 20060119721A1
• Time in Patent Office: 1,224 Days
• Field of Search: 348/296, 348/294, 348/207.99, 348/302, 348/308
• US Class Current: 348/296
• CPC Class Codes: H04N 25/531 by controlling rolling shutters in CMOS SSIS
• CPC Class Codes: H04N 25/745 Circuitry for generating timing or clock signals
• CPC Class Codes: H04N 25/76 Addressed sensors, e.g. MOS or CMOS sensors

Abstract

CMOS image sensor with a rolling shutter that uses two separate clocks. One of the clocks is used during normal operation. When timing is changed, the other clock is started and used during an interim period to avoid distortion in the image. After that interim period, the new clock timing is coupled to the original clock circuit.

Claims

1. An image sensor, comprising:

an array of image sensing elements; and

a controller for said array of image sensing elements, which produces clock signals to control said array of image sensing elements and which produces first clock signals to control a time of integration beginning and second clock signals at a second time to control a time of integration ending, said controller controlling said first clock signals to be produced at a same time as said second time for a different row during normal operation, and enabling control of a clock-changing operation to set said first clock signal to be produced at a time different than said second time,

wherein said controller includes first and second clock producing elements, said first clock producing element normally producing said first and second clock signals, and said second clock producing element producing an additional clock signal used as said different time.

2. A sensor as in claim 1, wherein said additional clock signal is formed according to specified formation characteristics, and said formation characteristics of said additional clock signal are used to drive said first clock producing elements during a clock period after an interim clock period.

3. A sensor as in claim 1, wherein said array of image sensing elements and said controller are formed of CMOS semiconductors.

4. A sensor as in claim 1, wherein said controller includes a processor which is programmed to produce said first and second clock signals.

5. A sensor as in claim 1, wherein said first clock signals and second clock signals operate at different clock speeds.