Phase change memory devices and systems, and related programming methods
First Claim
1. A method of performing a program operation in a phase change memory device comprising a plurality of phase change memory cells, the method comprising:
- (a) receiving program data to be programmed in selected memory cells among the plurality of phase change memory cells;
(b) sensing read data stored in the selected memory cells by detecting respective magnitudes of verify currents flowing through the selected memory cells when a verify read voltage is applied to the selected memory cells;
(c) determining whether the read data is identical to the program data; and
(d) upon determining that the program data for one or more of the selected memory cells is not identical to the corresponding read data, programming the one or more selected memory cells with the program data.
1 Assignment
0 Petitions
Accused Products
Abstract
A phase change memory device performs a program operation by receiving program data to be programmed in selected memory cells, sensing read data already stored in the selected memory cells by detecting respective magnitudes of verify currents flowing through the selected memory cells when a verify read voltage is applied to the selected memory cells, determining whether the read data is identical to the program data, and upon determining that the program data for one or more of the selected memory cells is not identical to the corresponding read data, programming the one or more selected memory cells with the program data.
76 Citations
41 Claims
-
1. A method of performing a program operation in a phase change memory device comprising a plurality of phase change memory cells, the method comprising:
-
(a) receiving program data to be programmed in selected memory cells among the plurality of phase change memory cells; (b) sensing read data stored in the selected memory cells by detecting respective magnitudes of verify currents flowing through the selected memory cells when a verify read voltage is applied to the selected memory cells; (c) determining whether the read data is identical to the program data; and (d) upon determining that the program data for one or more of the selected memory cells is not identical to the corresponding read data, programming the one or more selected memory cells with the program data. - View Dependent Claims (2, 3, 4, 5, 6, 7)
-
-
8. A method of performing a program operation in a phase change memory device comprising a plurality of phase change memory cells, the method comprising:
-
(a) receiving a plurality of program data bits to be programmed to selected memory cells among the plurality of memory cells; (b) sensing read data stored in the selected memory cells during a verify read section in which a verify current is supplied to each of the selected memory cells, wherein the magnitude of the verify current applied to each of the selected memory cells depends on a logic state of a corresponding data bit among the plurality of program data bits; (c) determining whether each of the plurality of program data bits is identical to a corresponding bit among the read data; (d) upon determining that each of the plurality of program data bits is identical to the corresponding bit among the read data, terminating the program operation; (e) upon determining that one or more of the plurality of program data bits is not identical to corresponding bits among the read data, programming the one or more of the plurality of program data bits to the corresponding selected memory cells during a program section; and (f) repeatedly performing a program loop comprising (b), (c), (d), and (e) until the each of the plurality of program data bits is identical to the corresponding bit among the read data or until a predetermined number of program loops have been performed. - View Dependent Claims (9, 10, 11)
-
-
12. A phase change memory device, comprising:
-
a memory cell array comprising a plurality of phase change memory cells arranged in rows and columns; a column select circuit adapted to select a subset of the columns in response to a column address; a data input/output (IO) buffer circuit adapted to temporarily store program data to be programmed to selected memory cells among the plurality of phase change memory cells in the memory cell array; a sense amplifier circuit adapted to supply respective verify currents to the selected memory cells via the selected columns during a verify read section of a program operation, wherein each of the respective verify currents has a magnitude corresponding to the program data to be programmed to a corresponding one of the selected memory cells; a control logic unit adapted to generate pulse signals for programming the selected memory cells during a program execution section of the program operation, wherein each individual pulse signal among the pulse signals is generated based on a determination that a bit among the program data is not identical to a corresponding bit of read data stored in a corresponding one of the selected memory cells to be programmed using the individual pulse signal; and
,a write driver circuit adapted to supply respective program currents to the selected columns using the pulse signals. - View Dependent Claims (13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39)
-
-
40. A system comprising:
-
a bus; a microprocessor connected to the bus; and a phase change memory device connected to the bus and adapted to store data processed or to be processed by the microprocessor; wherein the phase change memory device comprises a plurality of phase change memory cells and is adapted to perform a program operation by a method comprising; (a) receiving program data to be programmed in selected memory cells among the plurality of phase change memory cells; (b) sensing read data stored in the selected memory cells by detecting respective magnitudes of verify currents flowing through the selected memory cells when a verify read voltage is applied to the selected memory cells; (c) determining whether the read data is identical to the program data; (d) upon determining that the program data for one or more of the selected memory cells is not identical to the corresponding read data, programming the one or more selected memory cells with the program data.
-
-
41. A system comprising:
-
a bus; a microprocessor connected to the bus; and a phase change memory device connected to the bus and adapted to store data processed or to be processed by the microprocessor; wherein the phase change memory device comprises; a memory cell array comprising a plurality of phase change memory cells arranged in rows and columns; a column select circuit adapted to select a subset of the columns in response to a column address; a data input/output (IO) buffer circuit adapted to temporarily store program data to be programmed to selected memory cells among the plurality of phase change memory cells in the memory cell array; a sense amplifier circuit adapted to supply respective verify currents to the selected memory cells via the selected columns during a verify read section of a program operation, wherein each of the respective verify currents has a magnitude corresponding to the program data to be programmed to a corresponding one of the selected memory cells; a control logic unit adapted to generate pulse signals for programming the selected memory cells during a program execution section of the program operation, wherein each individual pulse signal among the pulse signals is generated based on a determination that a bit among the program data is not identical to a corresponding bit of read data stored in a corresponding one of the selected memory cells to be programmed using the individual pulse signal; and
,a write driver circuit adapted to supply respective program currents to the selected columns using the pulse signals.
-
Specification