Apparatus for controlling bitline bias voltage
First Claim
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1. An apparatus for controlling a bitline bias voltage, comprising:
- a detector for sensing the bitline bias voltage;
a bitline bias control signal generation circuit coupled to the detector for generating a bitline bias control signal in accordance with the sensed bitline bias voltage; and
a bitline bias voltage controller unit for controlling the bitline bias voltage in accordance with the bitline bias control signal, wherein the bitline bias control signal generation circuit includes a sensor for sensing the bitline bias control signal;
a pull up circuit for pulling up the bitline bias control signal when the sensed bitline bias control signal indicates that the bitline is coupling low and that the sensed bitline bias control signal is less than a first reference value; and
a pull down circuit for pulling down the bitline bias control signal when the sensed bitline bias control signal indicates that the bitline is coupling high and the sensed bitline bias control signal is greater than a second reference value.
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Abstract
Controlling a bitline bias voltage by sensing the bitline bias voltage, modifying a bitline bias control signal in accordance with the sensed bitline bias voltage, and controlling the bitline bias voltage in accordance with the modified bitline bias control signal. The modifying the bitline bias control signal is carried out by enabling a pull up circuit and disabling a pull down circuit in response to a first control signal and disabling the pull up circuit and enabling the pull down circuit in response to a second control signal.
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Citations
6 Claims
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1. An apparatus for controlling a bitline bias voltage, comprising:
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a detector for sensing the bitline bias voltage; a bitline bias control signal generation circuit coupled to the detector for generating a bitline bias control signal in accordance with the sensed bitline bias voltage; and a bitline bias voltage controller unit for controlling the bitline bias voltage in accordance with the bitline bias control signal, wherein the bitline bias control signal generation circuit includes a sensor for sensing the bitline bias control signal; a pull up circuit for pulling up the bitline bias control signal when the sensed bitline bias control signal indicates that the bitline is coupling low and that the sensed bitline bias control signal is less than a first reference value; and a pull down circuit for pulling down the bitline bias control signal when the sensed bitline bias control signal indicates that the bitline is coupling high and the sensed bitline bias control signal is greater than a second reference value. - View Dependent Claims (2, 3, 4, 5, 6)
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Specification
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Current AssigneeSanDisk Technologies LLC (Western Digital Corporation)
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Original AssigneeSanDisk Corporation (Western Digital Corporation)
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InventorsPan, Feng, Pham, Trung
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Primary Examiner(s)Pham; Ly D
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Application NumberUS11/617,531Publication NumberTime in Patent Office859 DaysField of Search365/185.18, 365/185.21, 365/185.25, 365/189.09, 365/189.11, 365/189.07, 365/189.21US Class Current365/185.21CPC Class CodesG11C 16/24 Bit-line control circuitsG11C 7/12 Bit line control circuits, ...
