Memory system and method with serial and parallel modes
First Claim
Patent Images
1. A memory system comprising:
- at least one memory bank;
interface circuitry operable with a plurality of modes, for connecting a plurality of inputs and a plurality of outputs to the at least one memory bank, the interface circuitry having a serial mode during which each of at least one input of the plurality of inputs operates as a respective serial input and each of at least one output of the plurality of outputs operates as a respective serial output, the interface circuitry having a parallel mode during which the plurality of inputs operate collectively as a parallel input and the plurality of outputs operate collectively as a parallel output.
16 Assignments
0 Petitions
Accused Products
Abstract
Methods and systems are provided that allow the method of access to one or more memory banks to be performed using serial access, or using parallel access. In serial mode, each link operates as an independent serial link. In contrast, during serial mode, the links operate in common as a parallel link. Where input and output controls are received independently for each link for serial mode, a single set of input and output controls is used in common by all of the links during parallel mode.
-
Citations
19 Claims
-
1. A memory system comprising:
-
at least one memory bank; interface circuitry operable with a plurality of modes, for connecting a plurality of inputs and a plurality of outputs to the at least one memory bank, the interface circuitry having a serial mode during which each of at least one input of the plurality of inputs operates as a respective serial input and each of at least one output of the plurality of outputs operates as a respective serial output, the interface circuitry having a parallel mode during which the plurality of inputs operate collectively as a parallel input and the plurality of outputs operate collectively as a parallel output. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16)
-
-
17. A method comprising:
-
reconfiguring a memory interface into a selected one of a serial mode and a parallel mode according to a data width control input; in serial mode, the memory interface functioning as at least one serial interface; in parallel mode, the memory interface functioning as a parallel interface. - View Dependent Claims (18, 19)
-
Specification