Method and system for synchronizing communications links in a hub-based memory system
First Claim
1. A memory hub comprising:
- downstream and upstream reception ports, each reception port operable in an initialization mode to synchronize reception of test data from a respective off-hub transmission port and further operable to enter a normal mode in response to receiving an enable command from the respective off-hub transmission port, each reception port operable to generate a completion signal in response to receiving inverted test data from the respective off hub transmission port and further operable to generate an enable signal in response to receiving the enable command from the respective off-hub transmission port; and
downstream and upstream transmission ports, each transmission port operable in the initialization mode to synchronize transmission of test data to a respective off-hub reception port and further operable to enter the normal mode in response to receiving an enable signal from a respective reception port of the memory hub, each transmission port operable to transmit inverted test data to the respective off-hub reception port in response to receiving a completion signal from the respective reception port of the memory hub and operable to generate an enable command for the respective off-hub reception port in response to receiving the enable signal from the respective reception port of the memory hub.
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Abstract
A method is disclosed for synchronizing communications links in a memory hub system. The system includes a system controller and a plurality of memory hubs coupled in series, with pairs of downstream and upstream links being coupled between adjacent modules and the controller. The method includes synchronizing each upstream and downstream link. In a clockwise order starting with the downstream link coupled between the controller and the first memory module, the next adjacent clockwise link is signaled that the prior clockwise link has been synchronized. The method detects through the upstream link coupled between the controller and the first memory module when all links have been synchronized. In a clockwise order starting with the downstream link coupled between the controller and the first memory module, each link is enabled. The method detects through the upstream link coupled between the controller and first memory module when all links have been enabled.
271 Citations
24 Claims
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1. A memory hub comprising:
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downstream and upstream reception ports, each reception port operable in an initialization mode to synchronize reception of test data from a respective off-hub transmission port and further operable to enter a normal mode in response to receiving an enable command from the respective off-hub transmission port, each reception port operable to generate a completion signal in response to receiving inverted test data from the respective off hub transmission port and further operable to generate an enable signal in response to receiving the enable command from the respective off-hub transmission port; and downstream and upstream transmission ports, each transmission port operable in the initialization mode to synchronize transmission of test data to a respective off-hub reception port and further operable to enter the normal mode in response to receiving an enable signal from a respective reception port of the memory hub, each transmission port operable to transmit inverted test data to the respective off-hub reception port in response to receiving a completion signal from the respective reception port of the memory hub and operable to generate an enable command for the respective off-hub reception port in response to receiving the enable signal from the respective reception port of the memory hub. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A memory module comprising:
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a plurality of memory devices; and a memory hub comprising; downstream and upstream reception ports, each reception port operable in an initialization mode to synchronize reception of test data from a respective off-hub transmission port and further operable to enter a normal mode in response to receiving an enable command from the respective off-hub transmission port, each reception port operable to generate a completion signal in response to receiving inverted test data from the respective off hub transmission port and further operable to generate an enable signal in response to receiving the enable command from the respective off-hub transmission port; and downstream and upstream transmission ports, each transmission port operable in the initialization mode to synchronize transmission of test data to a respective off-hub reception port and further operable to enter the normal mode in response to receiving an enable signal from a respective reception port of the memory hub, each transmission port operable to transmit inverted test data to the respective off-hub reception port in response to receiving a completion signal from the respective reception port of the memory hub and operable to generate an enable command for the respective off-hub reception port in response to receiving the enable signal from the respective reception port of the memory hub. - View Dependent Claims (11, 12, 13, 14)
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15. A memory system comprising:
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a system controller; a plurality of memory modules, each memory module being coupled to adjacent memory modules through respective high-speed communications links, at least one of the memory modules being coupled to the system controller through a respective high-speed communications link, and each memory module comprising; a plurality of memory devices; and a memory hub, comprising; downstream and upstream reception ports, each reception port operable in an initialization mode to synchronize reception of test data from a respective off-hub transmission port and further operable to enter a normal mode in response to receiving an enable command from the respective off-hub transmission port, each reception port operable to generate a completion signal in response to receiving inverted test data from the respective off-hub transmission port and further operable to generate the enable signal in response to receiving an enable command from the respective off-hub transmission port; and downstream and upstream transmission ports, each transmission port operable in the initialization mode to synchronize transmission of test data to a respective off-hub reception port and further operable to enter the normal mode in response to receiving an enable signal from a respective reception port of the memory hub, each transmission port operable to transmit inverted test data to the respective off-hub reception port in response to receiving a completion signal from the respective reception port of the memory hub and operable to generate an enable command for the respective off-hub reception port in response to receiving the enable signal from the respective reception port of the memory hub. - View Dependent Claims (16, 17, 18, 19)
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20. A computer system comprising:
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a processor; a system controller coupled to the processor through respective downstream and upstream high-speed communications links; a memory system, comprising; a system controller; a plurality of memory modules, each memory module being coupled to adjacent memory modules through respective high-speed communications links, at least one of the memory modules being coupled to the system controller through a respective high-speed communications link, and each memory module comprising; a plurality of memory devices; downstream and upstream reception ports, each reception port operable in an initialization mode to synchronize reception of test data from a respective off-hub transmission port and further operable to enter a normal mode in response to receiving an enable command from the respective off-hub transmission port, each reception port operable to generate a completion signal in response to receiving inverted test data from the respective off-hub transmission port and further operable to generate an enable signal in response to receiving the enable command from the respective off-hub transmission port; and downstream and upstream transmission ports, each transmission port operable in the initialization mode to synchronize transmission of test data to a respective off-hub reception port and further operable to enter the normal mode in response to receiving an enable signal from a respective reception port of the memory hub, each transmission port operable to transmit inverted test data to the respective off-hub reception port in response to receiving a completion signal from the respective reception port of the memory hub and operable to generate an enable command for the respective off-hub reception port in response to receiving the enable signal from the respective reception port of the memory hub. - View Dependent Claims (21, 22, 23, 24)
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Specification