Method, apparatus, and computer program of searching for clustering faults in semiconductor device manufacturing

• US 7,529,634 B2
• Filed: 12/01/2004
• Issued: 05/05/2009
• Est. Priority Date: 08/21/2000
• Status: Expired due to Fees

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Ushiku, Yukihiro, Mitsutake, Kunihiro
• Primary Examiner(s): Feliciano; Eliseo Ramos
• Assistant Examiner(s): O MALLEY, MARY CATHERINE
• Application Number:
  US10/999,938
• Publication Number:
  US 20050097481A1
• Time in Patent Office: 1,616 Days
• Field of Search: 702/33, 702 35- 36, 702 81- 84, 702 58- 59, 702117-118, 702/128, 702/179, 702/183, 702/185, 438 16- 17, 324/512, 324/520, 324/537, 700108-110, 700/121
• US Class Current: 702/58
• CPC Class Codes: H01L 22/20 Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/014 Solder alloys

Abstract

A method of searching for clustering faults is employed for semiconductor device manufacturing. The method enters data on faults present in a search target, calculates a frequency distribution of the faults in unit cells divided from the search target, approximates the frequency distribution by overlaying at least two discrete distribution functions, and searches for clustering faults according to weights of the discrete distribution functions on the frequency distribution.

Claims

1. A method of optimizing a number of redundant circuits, comprising:

entering the number of redundant circuits required to repair faults in chips divided from a wafer;

calculating a frequency distribution of the redundant circuits on the chips;

calculating a number of acceptable chips produced from the wafer based on a set number of the redundant circuits using the frequency distribution, each of the acceptable chips being defined as a chip having the redundant circuits whose number is equal to or less than the set number of the redundant circuits; and

calculating an optimum number of redundant circuits that maximizes the number of acceptable chips produced from the wafer according to a relationship between the number of the redundant circuits and the number of acceptable chips produced from the wafer.

2. The method of claim 1, wherein the set number of the redundant circuits is obtained by approximating the frequency distribution by overlaying at least two discrete distribution functions.

3. The method of claim 1, further comprising:

detecting the faults present in the wafer;

storing coordinates of the detected faults; and

converting the coordinates of the detected faults into the number of faults in the chips and coordinates of the chips.