Method, apparatus, and computer program of searching for clustering faults in semiconductor device manufacturing
First Claim
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1. A method of optimizing a number of redundant circuits, comprising:
- entering the number of redundant circuits required to repair faults in chips divided from a wafer;
calculating a frequency distribution of the redundant circuits on the chips;
calculating a number of acceptable chips produced from the wafer based on a set number of the redundant circuits using the frequency distribution, each of the acceptable chips being defined as a chip having the redundant circuits whose number is equal to or less than the set number of the redundant circuits; and
calculating an optimum number of redundant circuits that maximizes the number of acceptable chips produced from the wafer according to a relationship between the number of the redundant circuits and the number of acceptable chips produced from the wafer.
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Abstract
A method of searching for clustering faults is employed for semiconductor device manufacturing. The method enters data on faults present in a search target, calculates a frequency distribution of the faults in unit cells divided from the search target, approximates the frequency distribution by overlaying at least two discrete distribution functions, and searches for clustering faults according to weights of the discrete distribution functions on the frequency distribution.
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3 Claims
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1. A method of optimizing a number of redundant circuits, comprising:
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entering the number of redundant circuits required to repair faults in chips divided from a wafer; calculating a frequency distribution of the redundant circuits on the chips; calculating a number of acceptable chips produced from the wafer based on a set number of the redundant circuits using the frequency distribution, each of the acceptable chips being defined as a chip having the redundant circuits whose number is equal to or less than the set number of the redundant circuits; and calculating an optimum number of redundant circuits that maximizes the number of acceptable chips produced from the wafer according to a relationship between the number of the redundant circuits and the number of acceptable chips produced from the wafer. - View Dependent Claims (2, 3)
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