Address mapping table and method of storing mapping data in the same

• US 7,529,880 B2
• Filed: 12/29/2005
• Issued: 05/05/2009
• Est. Priority Date: 02/07/2005
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Chung, Hyun-Mo, Park, Chan-Ik, Kim, Hye-Young
• Primary Examiner(s): Elmore; Reba I
• Application Number:
  US11/319,280
• Publication Number:
  US 20060212674A1
• Time in Patent Office: 1,223 Days
• Field of Search: 711/103, 711/209, 711/221
• US Class Current: 711/103
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory

Abstract

A run level address mapping table and related method provides for storing address mapping data, which maps logical addresses to physical addresses in a flash memory using a flash translation layer. A first value is stored in the address mapping table, indicating an initial location for a run within a memory block, the run having at least two consecutive physical addresses. A second value is stored in the address mapping table, indicating a total size for the run.

Claims

1. An address mapping table adapted for use with a flash memory, the address mapping table comprising:

address mapping data mapping logical addresses to physical addresses in the flash memory using a flash translation layer, wherein the address mapping data comprises;

a first value indicating an initial location in the flash memory for a run, the run comprising at least consecutive physical addresses to which corresponding consecutive logical addresses are mapped; and

a second value indicating total size for the run.

2. The address mapping table of claim 1, wherein the address mapping table stores the address mapping data on a run entry basis beginning at the initial location.

3. The address mapping table of claim 2, wherein the flash translation layer calculates a plurality of logical addresses and a plurality of physical addresses corresponding to the run on the basis of the initial location and the total size of the run.

4. The address mapping table of claim 1, wherein only the total size of the run is updated when a modified version of the run having consecutive physical addresses continuous with the physical addresses of the run is stored in the address mapping table.

5. The address mapping table of claim 1, wherein the logical addresses are logical page values in the flash memory.

6. The address mapping table of claim 1, wherein the physical addresses are physical page values in the flash memory.

7. The address mapping table of claim 6, wherein each physical page value corresponds to at least one or more physical sector values.

8. A method of storing address mapping data in an address mapping table, the address mapping data mapping logical addresses to physical addresses in a flash memory using a flash translation layer, the method comprising:

storing a first value indicating an initial location for a run, the run comprising at least consecutive physical addresses to which corresponding consecutive logical addresses are mapped; and

storing a second value indicating a total size for the run.

9. The method of claim 8, wherein the address mapping data associated with a the run is stored on a run entry basis.

10. The method of claim 8, further comprising:

storing updated address mapping data in the address mapping table.

11. The method of claim 10, wherein storing the updated address mapping data comprises writing only a total size for an updated run in the address mapping table when the updated run has consecutive physical addresses continuous with the physical addresses of the stored run.

12. The method of claim 8, wherein the logical addresses are logical page values in the flash memory.

13. The method of claim 8, wherein the physical addresses are physical page values in the flash memory.

14. The method of claim 13, wherein each physical page value corresponds to at least one or more physical sector values.

15. The method of claim 14, the method further comprising:

upon having one or more empty physical sectors within the one or more physical sector values, performing a copy-back operation to the one or more empty physical sectors.

16. The method of claim 10, the method further comprising:

upon a change in the initial location or total size for a run, reconstructing the address mapping data according to a time sequence.

17. An address mapping table adapted for use with a flash memory using a flash translation layer, and comprising a plurality of entries for storing address mapping data related to a run, wherein the address mapping data comprises:

an initial physical page value indicating an initial location for the run; and

a consecutive physical page value indicating a number of consecutive physical page values following the initial physical page value in the run.

18. The address mapping table of claim 17, wherein the address mapping data further comprises:

an initial logical page value, wherein the initial logical page value is correlated by the flash translation layer to the initial physical page value of the run.

19. The address mapping table of claim 18, wherein the initial physical page value corresponds to at least one or more physical sector values.

20. An address mapping table adapted for use with a flash memory, the address mapping table comprising:

address mapping data mapping logical addresses to physical addresses in the flash memory using a flash translation layer,

wherein the address mapping data comprises;

a first value indicating an initial location in the flash memory for a run comprising at least consecutive physical addresses; and

a second value indicating total size for the run, wherein the total size for the run is determined by a number of the consecutive physical addresses mapped with consecutive logical addresses.

21. An address mapping table adapted for use with a flash memory, the address mapping table comprising:

address mapping data of the address mapping table, wherein each of the address mapping data comprises;

a first value indicating an initial location in the flash memory for a run; and

a second value indicating total size for the run,

wherein each of the address mapping data is stored on a basis of the run, and the run comprises a set of consecutive memory pages having consecutive physical addresses and corresponding consecutive logical addresses.