Scalable-chip-correct ECC scheme
First Claim
1. An apparatus comprising:
- an encoder coupled to receive input data and configured to generate corresponding codewords; and
a decoder coupled to receive codewords and detect an error in the codewords;
wherein each codeword comprises a plurality of b-bit portions including two or more b-bit portions that contain data, and further including a first set of b check bits and a second set of w check bits;
wherein b is an integer greater than one, and wherein the first set of b check bits is used to detect a magnitude of an error in a first b-bit portion of the plurality of b-bit portions, wherein the magnitude of the error indicates whether or not an error is detected and further indicates which bits within the first b-bit portion are in error, and wherein the second set of w check bits is used to locate which one of the plurality of b-bit portions is the first b-bit portion containing the error, wherein w is an integer greater than zero and less than b;
wherein the encoder is configured to generate the first set of b check bits responsive to the plurality of b-bit portions of the codeword excluding the b-bit portion that stores the first set of b check bits, and wherein the encoder is configured to generate the second set of w check bits for a given codeword responsive to the data in the codeword; and
wherein the decoder is configured to decode the first set of b check bits and the codeword to detect and error and the magnitude of the error, and wherein the decoder is configured to decode the second set of w check bits and the data in the code word to locate the first b-bit portion containing the error.
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Abstract
An apparatus comprises an encode circuit coupled to receive input data and configured to generate corresponding codewords and a decode circuit coupled to receive codewords and detect an error in the codewords (and may, in some cases, correct the error). Each codeword comprises a plurality of b-bit portions (b is an integer greater than one). Additionally, each codeword comprises a first set of b check bits used to detect a magnitude of an error in a b-bit portion of the plurality of b-bit portions. Each codeword further comprises a second set of w check bits used to locate which one of the plurality of b-bit portions is the b-bit portion containing the error (w is an integer greater than zero and less than b).
96 Citations
19 Claims
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1. An apparatus comprising:
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an encoder coupled to receive input data and configured to generate corresponding codewords; and a decoder coupled to receive codewords and detect an error in the codewords; wherein each codeword comprises a plurality of b-bit portions including two or more b-bit portions that contain data, and further including a first set of b check bits and a second set of w check bits; wherein b is an integer greater than one, and wherein the first set of b check bits is used to detect a magnitude of an error in a first b-bit portion of the plurality of b-bit portions, wherein the magnitude of the error indicates whether or not an error is detected and further indicates which bits within the first b-bit portion are in error, and wherein the second set of w check bits is used to locate which one of the plurality of b-bit portions is the first b-bit portion containing the error, wherein w is an integer greater than zero and less than b; wherein the encoder is configured to generate the first set of b check bits responsive to the plurality of b-bit portions of the codeword excluding the b-bit portion that stores the first set of b check bits, and wherein the encoder is configured to generate the second set of w check bits for a given codeword responsive to the data in the codeword; and wherein the decoder is configured to decode the first set of b check bits and the codeword to detect and error and the magnitude of the error, and wherein the decoder is configured to decode the second set of w check bits and the data in the code word to locate the first b-bit portion containing the error. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. An apparatus comprising:
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an encoder coupled to receive input data and configured to generate corresponding codewords; and a decoder coupled to receive codewords and detect an error in the codewords; wherein each codeword comprises a plurality of b-bit portions including two or more b-bit portions that contain data, and further including a first check symbol and a second check symbol; wherein b is an integer greater than one, each b-bit portion comprising a symbol that is an element of GF(2b), and wherein a first b-bit portion of the plurality of b-bit portions is a first check symbol, and wherein the encoder is configured to generate the first check symbol as a sum in GF(2b), of the remaining plurality of b-bit portions, and wherein a second b-bit portion of the plurality of b-bit portions comprises the second check symbol that is an element of GF(2w), wherein w is an integer greater than zero and less than b, and wherein the encoder is configured to generate the second check symbol to satisfy an equation in which each of the symbols in the code word, excluding the first check symbol, is multiplied by a different matrix having b columns and w rows, each of the columns comprising a symbol in GF(2w), and the sum of the multiplication results equaling zero, and wherein the first check symbol is used to detect a magnitude of an error in a first b-bit portion of the plurality of b-bit portions of the codeword, wherein the magnitude of the error indicates whether or not an error is detected and further indicates which bits within the first b-bit portion are in error, and wherein the second check symbol is used to locate which of the plurality of b-bit portions is the first b-bit portion that contains the error. - View Dependent Claims (12, 13, 14, 15)
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16. A method comprising:
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receiving input data in an integrated circuit, the integrated circuit comprising an encoder; and the encoder generating a corresponding codeword for the input data, wherein the codeword comprises a plurality of b-bit portions including two or more b-bit portions that contain input data, and further including a first set of b check bits and a second set of w check bits; and
wherein b is an integer greater than one, and wherein the first set of b check bits used to detect a magnitude of an error in a first b-bit portion of the plurality of b-bit portions, wherein the magnitude of the error indicates whether or not an error is detected and further indicates which bits within the first b-bit portion are in error, and wherein the second set of w check bits is used to locate which one of the plurality of b-bit portions is the first b-bit portion containing the error, wherein w is an integer greater than zero and less than b, and wherein generating the corresponding code word for the input data comprises;the encoder generating the first set of b check bits responsive to the plurality of b-bit portions of the codeword excluding the b-bit portion that stores the first set of b check bits; and the encoder generating the second set of w check bits for a given codeword responsive to the input data in the codeword. - View Dependent Claims (17, 18, 19)
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Specification