Creating and executing a graphical program with first model of computation that includes a structure supporting second model of computation

• US 7,530,052 B2
• Filed: 06/16/2004
• Issued: 05/05/2009
• Est. Priority Date: 05/14/2004
• Status: Active Grant

• Current Assignee: National Instruments Corporation (Emerson Electric Company)
• Original Assignee: National Instruments Corporation (Emerson Electric Company)
• Inventors: Kodosky, Jeffrey L., Rogers, Steven W., Hogan, Kevin, Andrade, Hugo A., Morrow, Gregory O., Limroth, John C.
• Primary Examiner(s): Dam; Tuan Q
• Assistant Examiner(s): Wang; Ben C
• Application Number:
  US10/869,656
• Publication Number:
  US 20050257195A1
• Time in Patent Office: 1,784 Days
• Field of Search: None
• US Class Current: 717/113
• CPC Class Codes: G06F 8/34 Graphical or visual programming

Abstract

System and method for creating and executing a graphical program. A first plurality of graphical program elements (GPEs) having a first model of computation (MoC), e.g., homogenous dataflow, are assembled in a graphical program in response to first input. A structure, including an interior portion, is displayed in the graphical program, indicating use of a second MoC, e.g., multi-rate dataflow, for GPEs within the interior portion. A second plurality of GPEs having the second MoC are assembled within the interior portion of the structure in response to second input. The second plurality of GPEs are converted into a new third plurality of GPEs having the first MoC, e.g., by parsing the second plurality of GPEs to determine multiple primitives according to the second MoC, determining the third plurality of GPEs based on the primitives, and assembling the third plurality of GPEs in the graphical program.

Claims

1. A memory medium that stores program instructions for creating and executing a graphical program, wherein the program instructions are executable to perform:

assembling a first plurality of graphical program elements in a graphical program in response to first input, wherein the assembled first plurality of graphical program elements have a first model of computation;

displaying a structure in the graphical program, wherein the structure comprises an interior portion, and wherein the structure indicates use of a second model of computation for graphical program elements comprised within the interior portion of the structure; and

assembling a second plurality of graphical program elements within the interior portion of the structure in response to second input, wherein the assembled second plurality of graphical program elements comprised within the interior portion of the structure have the second model of computation; and

converting the assembled second plurality of graphical program elements into a new third plurality of graphical program elements having the first model of computation.

2. The memory medium of claim 1, wherein the first model of computation specifies a homogenous data flow model of computation.

3. The memory medium of claim 1, wherein said converting comprises:

parsing the second plurality of graphical program elements to determine a plurality of primitives, wherein the plurality of primitives operate according to the second model of computation;

determining the third plurality of graphical program elements based on the plurality of primitives; and

assembling the determined third plurality of graphical program elements in the graphical program.

4. The memory medium of claim 3, wherein said assembling the determined third plurality of graphical program elements comprises:

interconnecting the third plurality of graphical program elements according to an execution partial order based on a topological analysis of the graphical program and/or the second plurality of graphical program elements.

5. The memory medium of claim 4, wherein said assembling the determined third plurality of graphical program elements comprises:

enclosing the determined third plurality of graphical program elements in the structure, wherein the structure operates with respect to the first plurality of graphical program elements in accordance with the first model of computation.

6. The memory medium of claim 2, wherein the second model of computation specifies a synchronous data flow (SDF) model of computation.

7. The memory medium of claim 6, wherein the structure comprises a multi-rate loop structure enclosing the second plurality of graphical program elements, and wherein at least two of the second plurality of graphical program elements have different execution rates.

8. The memory medium of claim 7, wherein the second plurality of graphical program elements comprise an SDF diagram.

9. The memory medium of claim 8, wherein the second plurality of graphical program elements comprise SDF nodes interconnected via one or more edges, and wherein each edge specifies a first-in, first-out (FIFO) buffer and a delay.

10. The memory medium of claim 9, wherein each SDF node is specified to consume a respective first number of tokens, and is further specified to produce a respective second number of tokens, and wherein the delay for each edge specifies an initial number of tokens residing on that edge.

11. The memory medium of claim 10, wherein the program instructions are further executable to perform:

computing a repetitions vector for the SDF diagram, wherein the repetitions vector specifies a respective number of times each SDF node should fire to consume all tokens.

12. The memory medium of claim 11, wherein the program instructions are further executable to perform:

computing a valid schedule for the SDF diagram based on the repetitions vector.

13. The memory medium of claim 12, wherein said computing the valid schedule for the SDF diagram is performed at compile time.

14. The memory medium of claim 12, wherein the program instructions are further executable to perform:

optimizing the valid schedule with respect to one or more of;

program memory;

buffer memory;

context switch overhead; and

performance.

15. The memory medium of claim 14, wherein said optimizing is performed based on a specified target platform.

16. The memory medium of claim 12, wherein said determining the third plurality of graphical program elements based on the plurality of primitives, and said interconnecting the third plurality of graphical program elements according to an execution partial order based on a topological analysis of the second graphical program and/or the second plurality of graphical program elements are performed based on the valid schedule.

17. The memory medium of claim 1, wherein the second model of computation specifies one or more of:

cyclostatic data flow; and

parameterized data flow.

18. The memory medium of claim 1, wherein the first model of computation enables specification of parallelism of graphical program elements.

19. The memory medium of claim 1, wherein the first model of computation specifies a single rate execution of graphical program elements.

20. The memory medium of claim 1, wherein the first model of computation does not include explicit feedback connections to implement looping.

21. The memory medium of claim 1,

wherein the first model of computation specifies a single rate execution of graphical program elements;

and

wherein the first model of computation does not include explicit feedback connections to implement looping.

22. The memory medium of claim 1, wherein the first model of computation comprises graphical structure nodes that specify looping, wherein the graphical structure nodes do not include explicit feedback connections to implement looping.

23. The memory medium of claim 1, wherein the first model of computation comprises graphical structure nodes that specify conditional branching of operations.

24. The memory medium of claim 1, wherein the second model of computation specifies a heterogeneous model of computation.

25. The memory medium of claim 1,

wherein the graphical program comprises a data flow diagram;

wherein the first model of computation comprises a first data flow semantics.

26. The memory medium of claim 1, wherein the first model of computation comprises a basis model of computation operable to implement the second model of computation.

27. The memory medium of claim 1, wherein the second model of computation supports a multi-rate execution of graphical program elements.

28. The memory medium of claim 1, wherein the second model of computation includes explicit feedback connections to implement looping.

29. The memory medium of claim 1,

wherein the second model of computation specifies a multi-rate execution of graphical program elements;

and

wherein the second model of computation includes explicit feedback connections to implement looping.

30. The memory medium of claim 1, wherein the second plurality of graphical program elements comprises a control block diagram utilizing control block notation.

31. The memory medium of claim 1, wherein the second plurality of graphical program elements comprises a simulation diagram, wherein at least a subset of the second plurality of graphical program elements comprise simulation nodes, and wherein the simulation diagram implements a simulation.

32. The memory medium of claim 31, wherein the simulation nodes support direct feed-through and indirect feed-through for inputs and outputs of the simulation nodes.

33. The memory medium of claim 31,

wherein at least one of the simulation nodes comprises a plurality of inputs and a plurality of outputs;

wherein a first output of the plurality of outputs requires only a subset of the plurality of inputs; and

wherein the least one of the simulation nodes is operable to fire upon reception of the subset of the plurality of inputs to generate the first output.

34. The memory medium of claim 31, wherein at least one simulation node of the simulation nodes supports a feedback cycle between an output of the simulation node and an input of the simulation node.

35. The memory medium of claim 34, wherein at least one simulation node of the simulation nodes supports a feedback cycle between an output of the simulation node and an input of the simulation node if:

the input of the simulation node has indirect feed-through to the output of the simulation node; and

/or

the input of the simulation node corresponds to a different iteration than the output of the simulation node.

36. The memory medium of claim 31, wherein at least one of the simulation nodes executes two or more times per execution of the simulation diagram.

37. The memory medium of claim 31, wherein the program instructions are further executable to perform:

computing a feed-through mapping of inputs to outputs for the simulation nodes; and

storing the feed-through mapping.

38. The memory medium of claim 31, wherein the program instructions are further executable to perform:

configuring one or more simulation parameters for the simulation diagram; and

storing the configured one or more simulation parameters;

wherein the configured one or more simulation parameters specify operation of the simulation diagram.

39. The memory medium of claim 31, wherein at least one of the simulation nodes represents a sub-simulation diagram, wherein the sub-simulation diagram comprises two or more additional simulation nodes.

40. The memory medium of claim 39, wherein the program instructions are further executable to perform:

configuring one or more simulation parameters for the sub-simulation diagram; and

storing the configured one or more simulation parameters;

wherein the configured one or more simulation parameters specify operation of the sub-simulation diagram.

41. The memory medium of claim 1, wherein the first model of computation supports only direct feed-through for inputs and outputs of graphical program elements.

42. The memory medium of claim 1, wherein the program instructions are further executable to perform:

executing the graphical program.

43. The memory medium of claim 42,

wherein the third plurality of graphical program elements comprises a companion diagram in accordance with the first model of computation and corresponds to the second plurality of graphical program elements;

and

wherein executing the graphical program comprises executing the companion diagram.

44. The memory medium of claim 42, wherein the program instructions are further executable to perform:

converting at least a portion of the graphical program into a form suitable for deployment on a programmable hardware element.

45. The memory medium of claim 44, wherein the program instructions are further executable to perform:

deploying the converted at least a portion of the graphical program onto the programmable hardware element; and

executing the graphical program, wherein said executing comprises executing the converted at least a portion of the third graphical program on the programmable hardware element.

46. The memory medium of claim 42,

wherein the graphical program comprises a plurality of interconnected nodes that visually indicate functionality of the graphical program.

47. The memory medium of claim 42,

wherein the graphical program comprises a heterogeneous graphical data flow program.

48. The memory medium of claim 42,

wherein the third graphical program is operable to perform one or more of:

an industrial automation function;

a process control function;

a test and measurement function.

49. The memory medium of claim 42,

wherein the graphical program comprises a block diagram portion and a user interface portion.

50. The memory medium of claim 49, wherein, during execution of the graphical program, the graphical user interface portion is displayed on a display of a first computer system and the block diagram executes on a second computer system.

51. The memory medium of claim 50, wherein said executing the graphical program comprises including highlighting each graphical program element in the graphical program while the graphical program element is executing.

52. The memory medium of claim 42, wherein the program instructions are further executable to perform:

providing debug information for the first plurality of graphical program elements in accordance with the first model of computation; and

providing debug information for the second plurality of the graphical program elements in accordance with the second model of computation.

53. The memory medium of claim 1, wherein the program instructions are further executable to perform:

receiving debug information for the first plurality of graphical program elements in accordance with the first model of computation; and

receiving debug information for the second plurality of graphical program elements in accordance with the second model of computation.

54. The memory medium of claim 1, wherein said converting comprises:

converting the second plurality of graphical program elements to a graph description; and

converting the graph description to the third plurality of graphical program elements.

55. The memory medium of claim 1, wherein the program instructions are further executable to perform:

displaying the third plurality of graphical program elements.

56. The memory medium of claim 1, wherein the program instructions are further executable to perform:

receiving user input invoking said converting, wherein said converting is performed in response to the user input.

57. The memory medium of claim 1, wherein the program instructions are further executable to perform:

compiling the graphical program, wherein said compiling comprises said converting.

58. A memory medium that stores program instructions for creating and executing a graphical program, wherein the program instructions are executable to perform:

assembling a first plurality of graphical program elements in the graphical program in response to first input, wherein the assembled first plurality of graphical program elements have a first model of computation;

assembling a second plurality of graphical program elements within the graphical program in response to second input, wherein the assembled second plurality of graphical program elements have the second model of computation;

compiling the graphical program, wherein said compiling comprises converting the assembled second plurality of graphical program elements into a new third plurality of graphical program elements having the first model of computation.

59. The memory medium of claim 58, wherein the program instructions are further executable to perform:

displaying a structure in the graphical program, wherein the structure comprises an interior portion, wherein the structure indicates use of a second model of computation for graphical program elements comprised within the interior portion of the structure.

60. The memory medium of claim 59, wherein the graphical program comprises a data flow diagram.

61. A memory medium that stores program instructions for creating and executing a graphical program, wherein the program instructions are executable to perform:

assembling a first plurality of graphical program elements in a graphical program in response to first input, wherein the assembled first plurality of graphical program elements have a first model of computation;

displaying a structure in the graphical program, wherein the structure comprises an interior portion, wherein the structure indicates use of a second model of computation for graphical program elements comprised within the interior portion of the structure; and

assembling a second plurality of graphical program elements within the interior portion of the structure in response to second input, wherein the assembled second plurality of graphical program elements comprised within the interior portion of the structure have the second model of computation;

converting the assembled second plurality of graphical program elements into a new third plurality of graphical program elements having the first model of computation;

wherein after said converting the graphical program comprises the first plurality of graphical program elements and the third plurality of graphical program elements, wherein the graphical program is executable according to the first model of computation.

62. The memory medium of claim 61, wherein the graphical program comprises a data flow diagram.