Providing variable sized contacts for coupling with a semiconductor device

• US 7,530,814 B2
• Filed: 09/25/2007
• Issued: 05/12/2009
• Est. Priority Date: 09/25/2007
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Ramaswamy, Chandrashekhar, Ruttan, Thomas G., Summers, Mark D.
• Primary Examiner(s): TA, THO DAC
• Application Number:
  US11/903,962
• Publication Number:
  US 20090081889A1
• Time in Patent Office: 595 Days
• Field of Search: 439/66, 439/862, 439/924.1
• US Class Current: 439/66
• CPC Class Codes: H01R 12/714 with contacts abutting directly the printed circuit; Button contacts therefore provided on the printed circuit
• CPC Class Codes: H01R 13/2442 with a single cantilevered beam
• CPC Class Codes: H05K 2201/0311 Metallic part with specific elastic properties, e.g. bent piece of metal as electrical contact
• CPC Class Codes: H05K 2201/1031 Surface mounted metallic connector elements
• CPC Class Codes: H05K 2201/10719 Land grid array [LGA]
• CPC Class Codes: H05K 3/326 the printed circuit having integral resilient or deformable parts, e.g. tabs or parts of flexible circuits H05K3/365 takes precedence
• CPC Class Codes: H05K 3/4015 using auxiliary conductive elements, e.g. pieces of metal foil, metallic spheres
• CPC Class Codes: H05K 7/1069 with spring contact pieces
• CPC Class Codes: Y02P 70/50 Manufacturing or production processes characterised by the final manufactured product

Abstract

In one embodiment, the present invention includes a circuit board having integrated contacts to mate with corresponding pads of a semiconductor device. At least some of the integrated contacts are of varying sizes to enable different contact resistances between the corresponding integrated contacts and pads, enabling reduced loading forces to adapt the semiconductor device to the circuit board. Other embodiments are described and claimed.

Claims

1. An apparatus comprising:

a circuit board having a plurality of integrated contacts integrated on a surface thereof to directly mate with corresponding pads of a semiconductor device, wherein some of the plurality of integrated contacts are of varying sizes, the varying sizes to enable different contact resistances between the corresponding integrated contacts and pads, wherein a first set of the plurality of integrated contacts are of a first height and a second set of the plurality of integrated contacts are of a second height, the first height greater than the second height, wherein the first set of integrated contacts are to be associated with power pads of the semiconductor device to enable communication of power from a power plane of the circuit board to the power pads of the semiconductor device, and the second set of integrated contacts are to be associated with input/output (I/O) pads of the semiconductor device to enable communication of signals from a signal plane of the circuit board to the I/O pads of the semiconductor device.

2. The apparatus of claim 1, wherein at least some of the first set of integrated contacts are of a first thickness and the second set of integrated contacts are of a second thickness, the first thickness greater than the second thickness.

3. The apparatus of claim 1, wherein the first set of integrated contacts are to directly mate with the power pads to realize a first contact resistance and the second set of integrated contacts are to directly mate with the I/O pads to realize a second contact resistance, the first contact resistance less than the second contact resistance.

4. The apparatus of claim 1, wherein the varying sizes enable a reduced load to mate the semiconductor device with the integrated contacts.

5. The apparatus of claim 1, further comprising a socket frame adapted to the circuit board, wherein the socket frame is sized to surround the integrated contacts, and wherein the semiconductor device is to be loaded into the socket frame with a force less than a force to load the semiconductor device into a socket having contacts of a uniform size.

6. The apparatus of claim 1, wherein the circuit board is to mate with the semiconductor device without a corresponding socket package.

7. The apparatus of claim 1, wherein the plurality of integrated contacts each include a pad portion to directly mate with a via of the circuit board.

8. A system comprising:

a semiconductor device having a plurality of power lands and a plurality of input/output (I/O) lands;

a motherboard having a contact field including a first plurality of contacts and a second plurality of contacts integrated on a surface of the motherboard, the first plurality of contacts to directly mate with the power lands and the second plurality of contacts to directly mate with the I/O lands, wherein the first plurality of contacts are sized differently than the second plurality of contacts; and

a socket frame adapted around the contact field and attached to the motherboard, the socket frame to constrain the semiconductor device laterally.

9. The system of claim 8, wherein the differently sized contacts enable a reduced load to adapt the semiconductor device to the motherboard as compared to a force to load the semiconductor device into a socket having contacts of a uniform size.

10. The system of claim 8, wherein the first plurality of contacts are of a first height and the second plurality of contacts are of a second height, the first height greater than the second height, wherein the first plurality of contacts directly mate with the power lands of the semiconductor device, and the second plurality of contacts directly mate with the I/O lands of the semiconductor device.

11. The system of claim 9, wherein at least some of the first plurality of contacts are of a first thickness and the second plurality of contacts are of a second thickness.

12. The system of claim 10, wherein the first plurality of contacts mate with the power lands to realize a first contact resistance and the second plurality of contacts mate with the I/O lands to realize a second contact resistance, the first contact resistance less than the second contact resistance.

13. A system comprising:

an integrated circuit (IC) having a first plurality of contacts and a second plurality of contacts, wherein the first plurality of contacts are sized differently than the second plurality of contacts, the first plurality of contacts of a first height and the second plurality of contacts of a second height, the first height greater than the second height, the first plurality of contacts corresponding to power contacts and the second plurality of contacts corresponding to input/output (I/O) contacts;

a motherboard having a contact field including a plurality of lands to mate with the first plurality of contacts and a second plurality of lands to mate with the second plurality of contacts; and

a socket frame adapted around the contact field and attached to the motherboard, the socket frame formed of a peripheral frame having an open interior to constrain the IC laterally.

14. The system of claim 13, wherein at least some of the first plurality of contacts are of a first thickness and the second plurality of contacts are of a second thickness, the first thickness greater than the second thickness.