Method of manufacturing semiconductor device with offset sidewall structure

• US 7,531,402 B2
• Filed: 05/01/2007
• Issued: 05/12/2009
• Est. Priority Date: 09/21/2001
• Status: Expired due to Fees

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Renesas Technology Corporation (Renesas Electronics Corporation)
• Inventors: Oda, Hidekazu, Ota, Kazunobu, Sayama, Hirokazu
• Primary Examiner(s): Le; Thao P.
• Application Number:
  US11/742,990
• Publication Number:
  US 20070207578A1
• Time in Patent Office: 742 Days
• Field of Search: 438/231, 257/E27.046, 257/E27.064, 257/E27.108, 257/E27.099
• US Class Current: 438/199
• CPC Class Codes: H01L 21/02164 the material being a silicon oxide, e.g. SiO2
• CPC Class Codes: H01L 21/0217 the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz H01L21/02126 and H01L21/0214 take precedence
• CPC Class Codes: H01L 21/265 producing ion implantation
• CPC Class Codes: H01L 21/28017 the insulator being formed after the semiconductor body, the semiconductor being silicon
• CPC Class Codes: H01L 21/28158 Making the insulator
• CPC Class Codes: H01L 21/823814 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 21/823857 with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
• CPC Class Codes: H01L 21/823864 with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/518 the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material

Abstract

A method of manufacturing a semiconductor device with NMOS and PMOS transistors is provided. The semiconductor device can lessen a short channel effect, can reduce gate-drain current leakage, and can reduce parasitic capacitance due to gate overlaps, thereby inhibiting a reduction in the operating speed of circuits. An N-type impurity such as arsenic is ion implanted to a relatively low concentration in the surface of a silicon substrate (1) in a low-voltage NMOS region (LNR) thereby to form extension layers (61). Then, a silicon oxide film (OX2) is formed to cover the whole surface of the silicon substrate (1). The silicon oxide film (OX2) on the side surfaces of gate electrodes (51-54) is used as an offset sidewall. Then, boron is ion implanted to a relatively low concentration in the surface of the silicon substrate (1) in a low-voltage PMOS region (LPR) thereby to form P-type impurity layers (621) later to be extension layers (62).

Claims

1. A method of manufacturing a semiconductor device comprising the steps of:

(a) preparing a semiconductor substrate having a major surface including a first NMOS region for forming a first NMOS transistor and a first PMOS region for forming a first PMOS transistor;

(b) forming a first gate insulating film in said first NMOS region and said first PMOS region and forming a first gate electrode and a second gate electrode on said first gate insulating film of said first NMOS region and said first PMOS region, respectively, and said first gate electrode and said second gate electrode each having side surfaces;

(c) after said step (b), forming a silicon oxide film on said side surface of said first gate electrode and said side surface of said second gate electrode;

(d) after said step (c), implanting an N-type impurity into said first NMOS region;

(e) after said step (d), forming an insulating film on said silicon oxide film formed on said side surface of said second gate electrode;

(f) after said step (e), implanting P-type impurity into said first PMOS region.