High performance system-on-chip passive device using post passivation process

• US 7,531,417 B2
• Filed: 05/27/2003
• Issued: 05/12/2009
• Est. Priority Date: 12/21/1998
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Megica Corporation (Chipbond Technology Corporation)
• Inventors: Lin, Mou-Shiung
• Primary Examiner(s): Pert; Evan
• Assistant Examiner(s): Tran; Tan N
• Application Number:
  US10/445,559
• Publication Number:
  US 20040029404A1
• Time in Patent Office: 2,177 Days
• Field of Search: 438/381, 438239-240, 438/250, 438/393, 438253-256, 438/396, 438/399, 438/238
• US Class Current: 438/381
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05624 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05644 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/13022 the bump connector being at least partially embedded in the surface
• CPC Class Codes: H01L 23/3192 Multilayer coating
• CPC Class Codes: H01L 23/522 including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
• CPC Class Codes: H01L 23/5222 Capacitive arrangements or effects of, or between wiring layers other capacitive arrangements H01L23/642
• CPC Class Codes: H01L 23/5223 Capacitor integral with wiring layers
• CPC Class Codes: H01L 23/5227 Inductive arrangements or effects of, or between, wiring layers other inductive arrangements H01L23/645
• CPC Class Codes: H01L 23/5228 Resistive arrangements or effects of, or between, wiring layers other resistive arrangements H01L23/647
• CPC Class Codes: H01L 23/5286 Arrangements of power or ground buses
• CPC Class Codes: H01L 23/5329 Insulating materials
• CPC Class Codes: H01L 23/60 Protection against electrostatic charges or discharges, e.g. Faraday shields
• CPC Class Codes: H01L 23/642 Capacitive arrangements H01L23/49589, H01L23/645, H01L23/647, H01L23/66 take precedence; capacitive effects between wiring layers on the semiconductor body H01L23/5222
• CPC Class Codes: H01L 23/645 Inductive arrangements H01L23/647, H01L23/66 take precedence
• CPC Class Codes: H01L 23/647 Resistive arrangements H01L23/66, H01L23/62 take precedence
• CPC Class Codes: H01L 24/03 Manufacturing methods
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 27/0676 comprising combinations of diodes, or capacitors or resistors
• CPC Class Codes: H01L 27/08 including only semiconductor components of a single kind
• CPC Class Codes: H01L 28/10 : Inductors
• CPC Class Codes: H01L 28/20 : Resistors
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01011 : Sodium [Na]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01014 : Silicon [Si]
• CPC Class Codes: H01L 2924/01019 : Potassium [K]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01024 : Chromium [Cr]
• CPC Class Codes: H01L 2924/01028 : Nickel [Ni]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01038 : Strontium [Sr]
• CPC Class Codes: H01L 2924/01042 : Molybdenum [Mo]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/01073 : Tantalum [Ta]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01075 : Rhenium [Re]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/04941 : TiN
• CPC Class Codes: H01L 2924/04953 : TaN
• CPC Class Codes: H01L 2924/05042 : Si3N4
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/10329 : Gallium arsenide [GaAs]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/1423 : Monolithic Microwave Integrated Circuit [MMIC]
• CPC Class Codes: H01L 2924/19015 : including thin film passive components
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19042 : being an inductor
• CPC Class Codes: H01L 2924/19043 : being a resistor
• CPC Class Codes: H01L 2924/19104 : on the semiconductor or solid-state device, i.e. passive-on-chip
• CPC Class Codes: H01L 2924/30105 : Capacitance
• CPC Class Codes: H01L 2924/3011 : Impedance
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding

Abstract

A system and method for forming post passivation passive components, such as resistors and capacitors, is described. High quality electrical components, are formed on a layer of passivation, or on a thick layer of polymer over a passivation layer.

Claims

1. A method of fabricating a system-on-chip structure, comprising:

providing a semiconductor substrate, a metallization structure over said semiconductor substrate, wherein said metallization structure comprises a first interconnect layer over said semiconductor substrate and a second interconnect layer over said first interconnect layer, a first dielectric layer between said first and second interconnect layers, and a passivation layer over said metallization structure and over said first dielectric layer, wherein said passivation layer comprises an oxide layer and a nitride layer;

forming a first polymer layer on said passivation layer, wherein said first polymer layer has a thickness between 2 and 150 micrometers and greater than a thickness of said passivation layer; and

forming a capacitor over said first polymer layer, wherein said capacitor comprises a lower plate on said first polymer layer, an upper plate over said lower plate, and a second dielectric layer between said upper and lower plates, wherein said lower plate has a thickness between 0.5 and 20 micrometers, said upper plate has a thickness between 0.5 and 20 micrometers, and said second dielectric layer has a thickness between 500 and 50,000 Angstroms, wherein forming said lower plate comprises depositing a first metal layer, followed by depositing a second metal layer over said first metal layer, followed by forming a first photoresist layer over said second metal layer, wherein a first opening in said first photoresist layer is over said second metal layer and exposes said second metal layer, followed by electroplating a third metal layer over said second metal layer exposed by said first opening, followed by removing said first photoresist layer, followed by removing said second metal layer not under said third metal layer, followed by removing said first metal layer not under said third metal layer, and wherein forming said upper plate comprises depositing a fourth metal layer, followed by depositing a fifth metal layer over said fourth metal layer, followed by forming a second photoresist layer over said fifth metal layer, wherein a second opening in said second photoresist layer is over said fifth metal layer and exposes said fifth metal layer, followed by electroplating a sixth metal layer over said fifth metal layer exposed by said second opening, followed by removing said second photoresist layer, followed by removing said fifth metal layer not under said sixth metal layer, followed by removing said fourth metal layer not under said sixth metal layer.

2. The method of claim 1, wherein said forming said first polymer layer comprises a coating process.

3. The method of claim 1, wherein said first polymer layer comprises polyimide.

4. The method of claim 1, wherein said first polymer layer comprises benzocyclobutene (BCB).

5. The method of claim 1, wherein said forming said first polymer layer comprises a curing process.

6. The method of claim 1, wherein said depositing said fourth metal layer comprises sputtering a titanium-containing layer having a thickness between 500 and 5,000 Angstroms.

7. The method of claim 1, wherein said depositing said fifth metal layer comprises sputtering a gold layer on said fourth metal layer, wherein said gold layer has a thickness between 300 and 3,000 Angstroms.

8. The method of claim 1, wherein said depositing said fifth metal layer comprises sputtering a copper layer on said fourth metal layer, wherein said copper layer has a thickness between 2,000 and 10,000 Angstroms.

9. The method of claim 1, wherein said depositing said first metal layer comprises sputtering a titanium-containing layer having a thickness between 500 and 5,000 Angstroms.

10. The method of claim 1, wherein said depositing said second metal layer comprises sputtering a gold layer on said first metal layer, wherein said gold layer has a thickness between 300 and 3,000 Angstroms.

11. The method of claim 1, wherein said depositing said second metal layer comprises sputtering a copper layer on said first metal layer, wherein said copper layer has a thickness between 2,000 and 10,000 Angstroms.

12. The method of claim 1, wherein said electroplating said sixth metal layer comprises electroplating a gold layer on said fifth metal layer exposed by said second opening, wherein said gold layer has a thickness between 1 and 20 micrometers.

13. The method of claim 1, wherein said electroplating said third metal layer comprises electroplating a gold layer on said second metal layer exposed by said first opening, wherein said gold layer has a thickness between 1 and 20 micrometers.

14. The method of claim 1, wherein said electroplating said third metal layer comprises electroplating a copper layer on said second metal layer exposed by said first opening, wherein said copper layer has a thickness between 3 and 20 micrometers.

15. The method of claim 1, wherein said electroplating said sixth metal layer comprises electroplating a copper layer on said fifth metal layer exposed by said second opening, wherein said copper layer has a thickness between 3 and 20 micrometers.

16. The method of claim 1, wherein said forming said lower plate further comprises, after said electroplating said third metal layer, electroplating a seventh metal layer on said third metal layer in said first opening, followed by said removing said first photoresist layer.

17. The method of claim 16, wherein said electroplating said seventh metal layer comprises electroplating a nickel layer on said third metal layer in said first opening, wherein said nickel layer has a thickness between 0.1 and 3 micrometers.

18. The method of claim 1, wherein said forming said upper plate further comprises, after said electroplating said sixth metal layer, electroplating a seventh metal layer on said sixth metal layer in said second opening, followed by said removing said second photoresist layer.

19. The method of claim 18, wherein said electroplating said seventh metal layer comprises electroplating a nickel layer on said sixth metal layer in said second opening, wherein said nickel layer has a thickness between 0.1 and 3 micrometers.

20. The method of claim 1, wherein said depositing said first metal layer comprises sputtering a titanium-tungsten-alloy layer having a thickness between 500 and 5,000 Angstroms.

21. The method of claim 1, wherein said depositing said fourth metal layer comprises sputtering a titanium-tungsten-alloy layer having a thickness between 500 and 5,000 Angstroms.

22. The method of claim 1 further comprising forming a second polymer layer over said capacitor.

23. The method of claim 1, wherein said second dielectric layer comprises SrTiO₃.

24. The method of claim 1, wherein said second dielectric layer comprises TEOS.

25. The method of claim 1, wherein said second dielectric layer comprises SiON.

26. The method of claim 1, wherein said second dielectric layer comprises Si₃N₄.

27. The method of claim 1, wherein said second dielectric layer comprises SiO₂.

28. A method of forming a system-on-chip structure, comprising:

providing a semiconductor substrate, a metallization structure over said semiconductor substrate, wherein said metallization structure comprises a first interconnect layer over said semiconductor substrate and a second interconnect layer over said first interconnect layer, a first dielectric layer between said first and second interconnect layers, and a passivation layer over said metallization structure and over said first dielectric layer, wherein said passivation layer comprises an oxide layer and a nitride layer; and

forming a capacitor over said passivation layer, wherein said capacitor comprises a lower plate over said passivation layer, an upper plate over said lower plate, and a second dielectric layer between said upper and lower plates, wherein said lower plate has a thickness between 0.5 and 20 micrometers, said upper plate has a thickness between 0.5 and 20 micrometers, and said second dielectric layer has a thickness between 500 and 50,000 Angstroms, wherein forming said lower plate comprises depositing a first metal layer, followed by depositing a second metal layer over said first metal layer, followed by forming a first photoresist layer over said second metal layer, wherein a first opening in said first photoresist layer is over said second metal layer and exposes said second metal layer, followed by electroplating a third metal layer over said second metal layer exposed by said first opening, followed by removing said first photoresist layer, followed by removing said second metal layer not under said third metal layer, followed by removing said first metal layer not under said third metal layer, and wherein forming said upper plate comprises depositing a fourth metal layer, followed by depositing a fifth metal layer over said fourth metal layer, followed by forming a second photoresist layer over said fifth metal layer, wherein a second opening in said second photoresist layer is over said fifth metal layer and exposes said fifth metal layer, followed by electroplating a sixth metal layer over said fifth metal layer exposed by said second opening, followed by removing said second photoresist layer, followed by removing said fifth metal layer not under said sixth metal layer, followed by removing said fourth metal layer not under said sixth metal layer.

29. The method of claim 28, wherein said depositing said first metal layer comprises sputtering a titanium-containing layer having a thickness between 500 and 5,000 Angstroms.

30. The method of claim 28, wherein said depositing said second metal layer comprises sputtering a gold layer on said first metal layer, wherein said gold layer has a thickness between 300 and 3,000 Angstroms.

31. The method of claim 28, wherein said depositing said second metal layer comprises sputtering a copper layer on said first metal layer, wherein said copper layer has a thickness between 2,000 and 10,000 Angstroms.

32. The method of claim 28, wherein said electroplating said third metal layer comprises electroplating a gold layer on said second metal layer exposed by said first opening, wherein said gold layer has a thickness between 1 and 20 micrometers.

33. The method of claim 28, wherein said electroplating said third metal layer comprises electroplating a copper layer on said second metal layer exposed by said first opening, wherein said copper layer has a thickness between 3 and 20 micrometers.

34. The method of claim 28, wherein said forming said lower plate further comprises, after said electroplating said third metal layer, electroplating a seventh metal layer on said third metal layer in said first opening, followed by said removing said first photoresist layer.

35. The method of claim 34, wherein said electroplating said seventh metal layer comprises electroplating a nickel layer on said third metal layer in said first opening, wherein said nickel layer has a thickness between 0.1 and 3 micrometers.

36. The method of claim 28, wherein said depositing said first metal layer comprises sputtering a titanium-tungsten-alloy layer having a thickness between 500 and 5,000 Angstroms.

37. The method of claim 28, wherein said depositing said fourth metal layer comprises sputtering a titanium-containing layer having a thickness between 500 and 5,000 Angstroms.

38. The method of claim 28, wherein said depositing said fifth metal layer comprises sputtering a gold layer on said fourth metal layer, wherein said gold layer has a thickness between 300 and 3,000 Angstroms.

39. The method of claim 28, wherein said depositing said fifth metal layer comprises sputtering a copper layer on said fourth metal layer, wherein said copper layer has a thickness between 2,000 and 10,000 Angstroms.

40. The method of claim 28, wherein said electroplating said sixth metal layer comprises electroplating a gold layer on said fifth metal layer exposed by said second opening, wherein said gold layer has a thickness between 1 and 20 micrometers.

41. The method of claim 28, wherein said electroplating said sixth metal layer comprises electroplating a copper layer on said fifth metal layer exposed by said second opening, wherein said copper layer has a thickness between 3 and 20 micrometers.

42. The method of claim 28, wherein said forming said upper plate further comprises, after said electroplating said sixth metal layer, electroplating a seventh metal layer on said sixth metal layer in said second opening, followed by said removing said second photoresist layer.

43. The method of claim 42, wherein said electroplating said seventh metal layer comprises electroplating a nickel layer on said sixth metal layer in said second opening, wherein said nickel layer has a thickness between 0.1 and 3 micrometers.

44. The method of claim 28, wherein said depositing said fourth metal layer comprises sputtering a titanium-tungsten-alloy layer having a thickness between 500 and 5,000 Angstroms.

45. The method of claim 28, wherein said second dielectric layer comprises SrTiO₃.

46. The method of claim 28, wherein said second dielectric layer comprises TEOS.

47. The method of claim 28, wherein said second dielectric layer comprises SiON.

48. The method of claim 28, wherein said second dielectric layer comprises Si₃N₄.

49. The method of claim 28, wherein said second dielectric layer comprises SiO₂.

50. The method of claim 28 further comprising forming a polymer layer on said passivation layer, followed by said forming said capacitor on said polymer layer.

51. The method of claim 50, wherein said polymer layer comprises polyimide.

52. The method of claim 28 further comprising forming a polymer layer over said capacitor.

53. The method of claims 52, wherein said polymer layer comprises polyimide.