Method of forming metal gate electrodes using sacrificial gate electrode material and sacrificial gate dielectric material

• US 7,531,437 B2
• Filed: 02/22/2006
• Issued: 05/12/2009
• Est. Priority Date: 09/30/2004
• Status: Expired due to Fees

• Current Assignee: Tahoe Research Limited (f/k/a Learndale Limited) (Vector Capital Corporation)
• Original Assignee: Intel Corporation
• Inventors: Shah, Uday, Chau, Robert S., Kavalieros, Jack, Doyle, Brian S., Brask, Justin K., Doczy, Mark
• Primary Examiner(s): Cao; Phat X
• Assistant Examiner(s): Kalam; Abul
• Application Number:
  US11/360,269
• Publication Number:
  US 20060138552A1
• Time in Patent Office: 1,175 Days
• Field of Search: 438/199, 438/149, 438/183, 438/585, 438/926, 438/974, 257/E21.444, 257/E21.453
• US Class Current: 438/585
• CPC Class Codes: H01L 21/845 including field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/1211 combined with field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/0673 oriented parallel to a substrate
• CPC Class Codes: H01L 29/41791 for transistors with a horizontal current flow in a vertical sidewall, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/66439 with a one- or zero-dimensional channel, e.g. quantum wire FET, in-plane gate transistor [IPG], single electron transistor [SET], striped channel transistor, Coulomb blockade transistor with an active layer made of a group 13/15 material H01L29/66469
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: Y10S 438/926 Dummy metallization
• CPC Class Codes: Y10S 438/974 Substrate surface preparation

Abstract

A semiconductor device comprising a semiconductor body having a top surface and a first and second laterally opposite sidewalls as formed on an insulating substrate is claimed. A gate dielectric is formed on the top surface of the semiconductor body and on the first and second laterally opposite sidewalls of the semiconductor body. A gate electrode is then formed on the gate dielectric on the top surface of the semiconductor body and adjacent to the gate dielectric on the first and second laterally opposite sidewalls of the semiconductor body. The gate electrode comprises a metal film formed directly adjacent to the gate dielectric layer. A pair of source and drain regions are then formed in the semiconductor body on opposite sides of the gate electrode.

Claims

1. A method of forming a semiconductor device comprising:

forming a sacrificial gate electrode over and around a semiconductor body having a top surface and a pair of laterally opposite sidewalls, wherein the portion of said semiconductor body surrounded by said sacrificial gate electrode defines a channel region of said semiconductor body;

etching away said sacrificial gate electrode to expose a sacrificial gate dielectric layer;

removing said sacrificial gate dielectric layer with an etchant to expose said channel region of said semiconductor body;

removing said sacrificial gate dielectric layer with an etchant to expose said channel region of said semiconductor body, wherein said etchant makes the surface of said channel region of said semiconductor body into a hydrophobic surface; and

converting said hydrophobic surface of said channel region into a hydrophilic surface;

depositing a gate dielectric layer on said top surface and sidewalls of said channel region of said semiconductor body; and

depositing a gate electrode material on said gate dielectric layer.

2. The method of claim 1 whereing forming a gate electrode material on said gate dielectric layer comprises:

forming a lower film having a midgap work function and an upper metal film.

3. A method of forming a semiconductor device comprising:

forming a sacrificial gate electrode material on a sacrificial gate dielectric layer over and around a semiconductor body having a top surface and a pair of laterally opposite sidewalls;

forming a hard mask material on said sacrificial gate electrode material;

patterning said sacrificial gate electrode material and said hard mask material into a hard mask and a sacrificial gate electrode wherein the portion of said semiconductor body beneath said sacrificial gate electrode defines a channel region of said semiconductor body;

forming a dielectric layer over and around said sacrificial gate electrode and said hard mask;

planarizing said dielectric layer until said hard mask is exposed and said dielectric layer is substantially planar with the top surface of said hard mask to form a planarized dielectric;

etching away said hard mask to reveal said sacrificial gate electrode;

etching away said sacrificial gate electrode to form an opening in said planarized dielectric layer to expose said sacrificial gate dielectric layer;

removing said sacrificial gate dielectric layer with an etchant to expose said channel region of said semiconductor body, wherein said etchant makes the surface of said channel region of said semiconductor body into a hydrophobic surface;

converting said hydrophobic surface of said channel region into a hydrophilic surface;

depositing a gate dielectric layer on said top surface and sidewalls of said hydrophilic surface of said channel region of said semiconductor body in said opening and on said top surface of said planarized dielectric;

blanket depositing a gate electrode material on said gate dielectric layer in said opening and on said gate dielectric layer on said dielectric layer; and

polishing said gate electrode material on said gate dielectric layer until said gate electrode material and said gate dielectric layer are completely removed from the top surface of said dielectric layer to form a gate electrode and a gate dielectric layer.

4. The method of claim 3 wherein said gate electrode material comprises a lower film having a midgap work function and an upper metal film.

5. The method of claim 4 wherein said midgap work function material is selected from the group consisting of the carbides or nitrides of titanium or tantalum.

6. The method of claim 4 wherein said upper metal film metal is selected from the group consisting of copper and tungsten.

7. The method of claim 3 wherein converting said hydrophobic surface of said channel region into said hydrophilic surface comprises exposing said hydrophobic surface to a solution comprising hydrogen peroxide.

8. The method of claim 3 wherein said gate dielectric layer is formed by atomic layer deposition.

9. The method of claim 8 wherein said atomic layer deposition comprises exposing said hydrophilic surface of said semiconductor body to a metal halide.

10. The method of claim 9 wherein said metal halide is hafnium tetrachloride (HfCl₄).