Semiconductor device including a strained superlattice between at least one pair of spaced apart stress regions

• US 7,531,828 B2
• Filed: 07/13/2006
• Issued: 05/12/2009
• Est. Priority Date: 06/26/2003
• Status: Active Grant

• Current Assignee: Atomera Incorporated
• Original Assignee: Mears Technologies Incorporated
• Inventors: Kreps, Scott A., Mears, Robert J.
• Primary Examiner(s): Pham; Long
• Application Number:
  US11/457,269
• Publication Number:
  US 20070012909A1
• Time in Patent Office: 1,034 Days
• Field of Search: 257/20, 257/23, 257/24, 257/27
• US Class Current: 257/20
• CPC Class Codes: H01L 29/1054 with a variation of the composition, e.g. channel with strained layer for increasing the mobility
• CPC Class Codes: H01L 29/152 with quantum effects only in vertical direction, i.e. layered structures with quantum effects solely resulting from vertical potential variation
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence

Abstract

A semiconductor device may include at least one pair of spaced apart stress regions, and a strained superlattice layer between the at least one pair of spaced apart stress regions and including a plurality of stacked groups of layers. Each group of layers of the strained superlattice layer may include a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.

Claims

1. A semiconductor device comprising:

at least one pair of spaced apart stress regions; and

a strained superlattice layer between said at least one pair of spaced apart stress regions and comprising a plurality of stacked groups of layers;

each group of layers of said strained superlattice layer comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions, and at least some semiconductor atoms from opposing base semiconductor portions being chemically bound together with the chemical bonds traversing the at least one non-semiconductor monolayer therebetween;

wherein the non-semiconductor is selected from the group consisting of at least one of oxygen, nitrogen, fluorine, and carbon.

2. The semiconductor device of claim 1 wherein said at least one pair of spaced apart stress regions comprises at least one pair of source and drain regions.

3. The semiconductor device of claim 1 wherein at least one of said stress regions has a canted surface adjacent opposing portions of said strained superlattice.

4. The semiconductor device of claim 1 wherein at least one of said stress regions comprises silicon and germanium.

5. The semiconductor device of claim 1 further comprising a semiconductor substrate below said at least one pair of spaced apart stress regions and said strained superlattice layer.

6. The semiconductor device of claim 1 wherein said strained superlattice layer has a compressive strain.

7. The semiconductor device of claim 1 wherein said strained superlattice layer has a tensile strain.

8. The semiconductor device of claim 1 wherein said strained superlattice layer has a common energy band structure therein.

9. The semiconductor device of claim 1 wherein each base semiconductor portion comprises silicon.

10. The semiconductor device of claim 1 wherein each base semiconductor portion comprises a base semiconductor selected from the group consisting of Group IV semiconductors, Group III-V semiconductors, and Group II-VI semiconductors.

11. The semiconductor device of claim 1 wherein each non-semiconductor monolayer comprises oxygen.

12. The semiconductor device of claim 1 wherein each non-semiconductor monolayer is a single monolayer thick.

13. The semiconductor device of claim 1 wherein each base semiconductor portion is less than eight monolayers thick.

14. The semiconductor device of claim 1 wherein said strained superlattice layer further has a substantially direct energy bandgap.

15. The semiconductor device of claim 1 wherein said strained superlattice layer further comprises a base semiconductor cap layer on an uppermost group of layers.

16. The semiconductor device of claim 1 wherein all of said base semiconductor portions are a same number of monolayers thick.

17. The semiconductor device of claim 1 wherein at least some of said base semiconductor portions are a different number of monolayers thick.

18. A semiconductor device comprising:

at least one pair of source and drain stress regions; and

a strained superlattice layer between said at least one pair of spaced apart source and drain stress regions and comprising a plurality of stacked groups of layers;

each group of layers of said strained superlattice layer comprising a plurality of stacked base silicon monolayers defining a base silicon portion and at least one oxygen monolayer constrained within a crystal lattice of adjacent base silicon portions, and at least some silicon atoms from opposing base silicon portions being chemically bound together with the chemical bonds traversing the at least one oxygen monolayer therebetween.

19. The semiconductor device of claim 18 wherein at least one of said source and drain stress regions has a canted surface adjacent opposing portions of said strained superlattice.

20. The semiconductor device of claim 18 wherein at least one of said source and drain stress regions comprises silicon and germanium.

21. The semiconductor device of claim 18 further comprising a semiconductor substrate below said at least one pair of spaced apart source and drain stress regions and said strained superlattice layer.

22. The semiconductor device of claim 18 wherein said strained superlattice layer has a common energy band structure therein.

23. A semiconductor device comprising:

at least one pair of spaced apart stress regions; and

a strained layer between said at least one pair of spaced apart stress regions and comprising a plurality of stacked base semiconductor portions and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions, and at least some semiconductor atoms from opposing base semiconductor portions being chemically bound together with the chemical bonds traversing the at least one non-semiconductor monolayer therebetween;

wherein the non-semiconductor is selected from the group consisting of at least one of oxygen, nitrogen, fluorine, and carbon.

24. The semiconductor device of claim 23 wherein said at least one pair of spaced apart stress regions comprises at least one pair of source and drain regions.

25. The semiconductor device of claim 23 wherein at least one of said stress regions has a canted surface adjacent opposing portions of said strained layer.

26. The semiconductor device of claim 23 wherein at least one of said stress regions comprises silicon and germanium.

27. The semiconductor device of claim 23 further comprising a semiconductor substrate below said at least one pair of spaced apart stress regions and said strained layer.