Semiconductor device including a memory cell with a negative differential resistance (NDR) device

• US 7,531,850 B2
• Filed: 05/30/2006
• Issued: 05/12/2009
• Est. Priority Date: 06/26/2003
• Status: Active Grant

• Current Assignee: Atomera Incorporated
• Original Assignee: Mears Technologies Incorporated
• Inventors: Blanchard, Richard A.
• Primary Examiner(s): Tran; Thien F
• Application Number:
  US11/420,876
• Publication Number:
  US 20060202189A1
• Time in Patent Office: 1,078 Days
• Field of Search: 257/15, 257/18, 257/22, 257/28, 257/107, 257/115, 257/133, 257/157
• US Class Current: 257/107
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: H01L 29/151 Compositional structures H01L29/157 and H01L29/158 take precedence
• CPC Class Codes: H01L 29/152 with quantum effects only in vertical direction, i.e. layered structures with quantum effects solely resulting from vertical potential variation
• CPC Class Codes: H01L 29/74 Thyristor-type devices, e.g. having four-zone regenerative action two-terminal thyristors H01L29/87

Abstract

A semiconductor device may include at least one memory cell comprising a negative differential resistance (NDR) device and a control gate coupled thereto. The NDR device may include a superlattice including a plurality of stacked groups of layers, with each group of layers of the superlattice including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.

Claims

1. A semiconductor device comprising:

at least one memory cell comprising a negative differential resistance (NDR) device and a control gate coupled thereto;

said NDR device comprising a superlattice including a plurality of stacked groups of layers with each group of layers of said superlattice comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.

2. The semiconductor device of claim 1 wherein said NDR device comprises a thyristor.

3. The semiconductor device of claim 2 wherein said thyristor comprises a plurality of stacked semiconductor layers having alternating first and second conductivity types;

and wherein an uppermost layer of said stack of semiconductor layers comprises said superlattice.

4. The semiconductor device of claim 3 wherein at least one other layer of said plurality of stacked semiconductor layers beneath said uppermost layer also comprises the superlattice.

5. The semiconductor device of claim 3 wherein said thyristor further comprises a voltage reference contact on said uppermost layer of said plurality of stacked semiconductor layers.

6. The semiconductor device of claim 1 wherein said at least one memory cell further comprises at least one access transistor coupled to said NDR device.

7. The semiconductor device of claim 1 wherein said at least one memory cell comprises a plurality thereof.

8. The semiconductor device of claim 1 wherein said base semiconductor portion comprises silicon.

9. The semiconductor device of claim 1 wherein said at least one non-semiconductor monolayer comprises oxygen.

10. The semiconductor device of claim 1 wherein said at least one non-semiconductor monolayer comprises a non-semiconductor selected from the group consisting essentially of oxygen, nitrogen, fluorine, and carbon-oxygen.

11. The semiconductor device of claim 1 wherein said at least one non-semiconductor monolayer is a single monolayer thick.

12. The semiconductor device of claim 1 wherein all of said base semiconductor portions are a same number of monolayers thick.

13. The semiconductor device of claim 1 wherein at least some of said base semiconductor portions are a different number of monolayers thick.

14. The semiconductor device of claim 1 wherein opposing base semiconductor portions in adjacent groups of layers of said at least one superlattice are chemically bound together.

15. A semiconductor device comprising:

at least one memory cell comprising a thyristor, a control gate coupled to said thyristor, and an access transistor coupled to said thyristor;

said thyristor comprising a plurality of stacked semiconductor layers having alternating first and second conductivity types, and at least one layer of said stack of semiconductor layers comprising a superlattice;

said superlattice including a plurality of stacked groups of layers with each group of layers of said superlattice comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.

16. The semiconductor device of claim 15 wherein said at least one layer of said stack of semiconductor layers comprises an uppermost layer of said plurality of stacked semiconductor layers.

17. The semiconductor device of claim 16 wherein said thyristor further comprises a voltage reference contact on said uppermost layer of said plurality of stacked semiconductor layers.

18. The semiconductor device of claim 15 wherein said base semiconductor portion comprises silicon;

and wherein said at least one non-semiconductor monolayer comprises oxygen.

19. The semiconductor device of claim 15 wherein opposing base semiconductor portions in adjacent groups of layers of said at least one superlattice are chemically bound together.

20. A semiconductor device comprising:

a thyristor comprising plurality of stacked semiconductor layers having alternating first and second conductivity types; and

a control gate coupled to said thyristor;

at least one of said layers of said stack of semiconductor layers comprising a superlattice including a plurality of stacked groups of layers with each group of layers of said superlattice comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.

21. The semiconductor device of claim 20 wherein said at least one layer of said stack of semiconductor layers comprises an uppermost layer of said plurality of stacked semiconductor layers.

22. The semiconductor device of claim 21 further comprising a voltage reference contact on said uppermost layer of said plurality of stacked semiconductor layers.

23. The semiconductor device of claim 20 wherein said base semiconductor portion comprises silicon;

and wherein said at least one non-semiconductor monolayer comprises oxygen.

24. The semiconductor device of claim 20 wherein opposing base semiconductor portions in adjacent groups of layers of said superlattice are chemically bound together.