High voltage transistor and method for fabricating the same

• US 7,531,872 B2
• Filed: 06/15/2007
• Issued: 05/12/2009
• Est. Priority Date: 09/08/2004
• Status: Active Grant

• Current Assignee: Magnachip Semiconductor Limited (Magnachip Semiconductor)
• Original Assignee: Magnachip Semiconductor Limited (Magnachip Semiconductor)
• Inventors: Ju, Jae-II
• Primary Examiner(s): Richards; N Drew
• Assistant Examiner(s): Singal; Ankush K
• Application Number:
  US11/818,647
• Publication Number:
  US 20070252200A1
• Time in Patent Office: 697 Days
• Field of Search: 257500-502, 257/330, 257/E27.064, 257/60, 257/68, 257/302, 257/328, 257/329, 257/374, 257/E21.018, 257/E21.383, 257/E21.41, 257/E21.418, 257/E21.447, 257/E21.612, 257/E21.629, 257/E21.652, 257/E27.056, 257/57, 257/61, 257 66- 72, 257 84- 85, 257/93, 257/140, 257/146, 257/265, 257/347, 257/357, 257/350, 257/368, 257/509, 257/511, 257/546, 257/272, 257/392, 257/499, 257/E21.56, 257/E21.705, 257/E25.01, 257/E27.001
• US Class Current: 257/330
• CPC Class Codes: H01L 21/823885 with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface with a current flow parallel to the substrate surface H01L21/823821
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7809 having both source and drain contacts on the same surface, i.e. Up-Drain VDMOS transistors
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A high voltage transistor operating through a high voltage and a method for fabricating the same are provided. The high voltage transistor includes: an insulation layer on a substrate; an N⁺-type drain junction region on the insulation layer; an N⁻-type drain junction region on the N⁺-type drain junction region; a P⁻-type body region provided in a trench region of the N⁻-type drain junction region; a plurality of gate patterns including a gate insulation layer and a gate conductive layer in other trench regions bordered by the P⁻-type body region and the N⁻-type drain junction region; a plurality of source regions contacted to a source electrode on the P⁻-type body region; and a plurality of N⁺-type drain regions contacted to the N⁻-type drain junction region and individual drain electrodes.

Claims

1. A high voltage transistor, comprising:

a single insulation layer on a substrate;

an N⁺-type drain junction region on the single insulation layer;

an N⁻

-type drain junction region on the N⁺-type drain junction region;

a P⁻

-type body region provided in a first trench region of the N⁻

-type drain junction region;

a plurality of first gate patterns including a first gate insulation layer and a first gate conductive layer in other trench regions bordered by the P⁻

-type body region and the N⁻

-type drain junction region;

a plurality of first source regions contacted to a first source electrode on the P⁻

-type body region;

a plurality of N⁺-type drain regions contacted to the N⁻

-type drain junction region and individual drain electrodes;

a P⁺-type drain junction region formed on the single insulation layer, wherein the P⁺-type drain junction region is formed to be apart from the N⁺-type drain junction region;

a P⁻

-type drain junction region formed on the P⁺-type drain junction region;

an N⁻

-type body region provided in a second trench region inside of the P⁻

-type drain junction region;

a plurality of second gate patterns including a second gate insulation layer and a second gate conductive layer in other trench regions bordered by the N⁻

-type body region and the P⁻

-type drain junction region;

a plurality of second source regions contacted to a second source electrode on the N⁻

-type body region; and

a plurality of P⁺-type drain regions contacted to the P⁻

-type drain junction region and individual drain electrodes.

2. The high voltage transistor of claim 1, wherein the plurality of first source regions include a P⁺-type source contact region contacted to the first source electrode and a plurality of N⁺-type source regions formed in a manner to surround the P⁺-type source contact region.

3. The high voltage transistor of claim 1, wherein the plurality of second source regions include an N⁺-type source contact region contacted to the second source electrode and a plurality of P⁺-type source regions formed in a manner to surround the N⁺-type source contact region.