Multi-chip package (MCP) with a conductive bar and method for manufacturing the same

• US 7,531,890 B2
• Filed: 05/16/2005
• Issued: 05/12/2009
• Est. Priority Date: 12/06/2001
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Kim, Gu-Sung
• Primary Examiner(s): Ghyka; Alexander G
• Assistant Examiner(s): Roman; Angel
• Application Number:
  US11/131,253
• Publication Number:
  US 20050205968A1
• Time in Patent Office: 1,457 Days
• Field of Search: 257/686, 257/777, 257/E23.141, 257/E23.01, 257/E29.111, 257/621, 257/723, 257/E29.112, 257/725, 438/109
• US Class Current: 257/621
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2224/02 Bonding areas; Manufacturing methods related thereto
• CPC Class Codes: H01L 2224/02372 connecting to a via connection in the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/02379 Fan-out arrangement
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05001 Internal layers
• CPC Class Codes: H01L 2224/05008 Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body, e.g.
• CPC Class Codes: H01L 2224/05022 the internal layer being at least partially embedded in the surface
• CPC Class Codes: H01L 2224/05024 the internal layer being disposed on a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05548 Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05569 the external layer being disposed on a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/13025 the bump connector being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/16146 the bump connector connecting to a via connection in the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/24011 Deposited, e.g. MCM-D type
• CPC Class Codes: H01L 2224/24145 the bodies being stacked
• CPC Class Codes: H01L 2224/24225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/24996 being formed on an item to be connected not being a semiconductor or solid-state body
• CPC Class Codes: H01L 2224/24998 Reinforcing structures, e.g. ramp-like support
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/9201 Forming connectors during the connecting process, e.g. in-situ formation of bumps
• CPC Class Codes: H01L 23/3114 : the device being a chip scale package, e.g. CSP
• CPC Class Codes: H01L 23/481 : Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 24/02 : Bonding areas on insulating substrates, e.g. chip carriers, H01L23/49816, H01L23/49838, H01L23/5389; Manufacturing methods related thereto
• CPC Class Codes: H01L 24/03 : Manufacturing methods
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/24 : of an individual high density interconnect connector
• CPC Class Codes: H01L 24/82 : by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI] interconnection structure between a plurality of semiconductor chips H01L23/5389
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 2924/0001 : Technical content checked by a classifier

Abstract

A multi-chip package (MCP) is provided. The MCP comprises a plurality of stacked semiconductor chips, each including a chip pad and a first insulating layer overlying the chip pad with an opening to expose a portion of the chip pad. Each chip additionally includes a pad redistribution line formed on the first insulating layer and a second insulating layer covering the pad redistribution line. A via hole is formed through the chip, the first insulating layer, a pad redistribution line and the second insulating layer. The MCP further includes a protective layer formed on the bottom of the lowest semiconductor chip. The protective layer includes a conductive pad formed opposite the bottom of the lowest semiconductor chip. A conductive bar extends through the via holes of the stacked semiconductor chips, from the conductive pad, and is electrically connected to the pad redistribution line of the stacked semiconductor chips.

Claims

1. A multi-chip package (MCP), comprising:

a plurality of stacked semiconductor chips, each chip including;

a chip pad on a main surface thereof;

a first insulating layer overlying the chip pad, the first insulating layer having an opening to expose a portion of the chip pad;

a pad redistribution line formed on the first insulating layer;

a second insulating layer covering the pad redistribution line,

wherein a via hole is formed through the chip, the first insulating layer, the pad redistribution line and the second insulating layer;

a protective layer formed on the bottom of the lowest semiconductor chip, the protective layer including a conductive pad formed opposite the bottom of the lowest semiconductor chip;

a conductive bar extending through the via holes of the stacked semiconductor chips, from the conductive pad, and being electrically connected to the pad redistribution line of the stacked semiconductor chips.

2. The MCP of claim 1, wherein the conductive bar is electrically connected to the pad redistribution line by a plating layer.

3. The MCP of claim 1, further comprising an external connection terminal attached to the conductive pad.

4. The MCP of claim 1, further comprising an adhesive layer interposed between the stacked semiconductor chips.

5. The MCP of claim 4, wherein the adhesive layer comprises elastomer.

6. The MCP of claim 1, wherein the conductive bar has a Ni coating layer formed thereon.

7. The MCP of claim 1, wherein each of the semiconductor chips is back lapped to reduce a total thickness of the MCP by thinning the bottom of each of the semiconductor chips.

8. The MCP of claim 1, further comprising a cap layer attached to the uppermost semiconductor chip.

9. The MCP of claim 1, wherein each chip further comprises a passivation layer disposed between the main surface and the first insulating layer.

10. The MCP of claim 1, wherein a top surface of the protective layer extends contiguously from one end to another end of the bottom of the lowest semiconductor chip.

11. The MCP of claim 1, wherein the conductive pad included in the protective layer is formed in a bottom portion of the protective layer to provide an external connection.

12. The MCP of claim 11, wherein the protective layer is permanently attached to the bottom of the lowest semiconductor chip.

13. The MCP of claim 1, wherein the protective layer comprises polyimide.

14. A semiconductor chip for manufacturing a MCP, the chip comprising:

a chip pad on a main surface thereof;

a passivation layer formed overlying the chip pad, the passivation layer having a first opening to expose a portion of the chip pad;

a first insulating layer overlying the passivation layer, the first insulating layer having a second opening to expose the portion of the chip pad;

a pad redistribution line formed on the first insulating layer; and

a second insulating layer covering the pad redistribution line,

wherein a via hole is formed through the chip, the first insulating layer, the pad redistribution line and the second insulating layer.

15. A multi-chip package (MCP), comprising:

a plurality of stacked semiconductor chips, each chip including;

a chip pad on a main surface thereof;

a first insulating layer overlying the chip pad, the first insulating layer having an opening to expose a portion of the chip pad;

a pad redistribution line formed on the first insulating layer; and

a second insulating layer covering the pad redistribution line,

wherein a via hole is formed through each of the chips, each of the first insulating layers, each of the pad redistribution lines, and each of the second insulating layers;

a protective layer formed on the bottom of the lowest semiconductor chip, the protective layer including a conductive pad formed opposite the bottom of the lowest semiconductor chip;

a conductive bar extending through the via holes of the stacked semiconductor chips, from the conductive pad, and being electrically connected to each of the pad redistribution lines of the stacked semiconductor chips; and

an electroplating layer interconnecting the conductive bar and each of the pad redistribution lines, wherein the electroplating layer is formed after insertion of the conductive bar through each of the stacked semiconductor chips and fills an open space surrounding the conductive bar.

16. The MCP of claim 15, wherein the protective layer is contiguously formed from one end to another end of the bottom of the lowest semiconductor chip.

17. The MCP of claim 15, wherein the conductive pad included in the protective layer is formed in a bottom portion of the protective layer to provide an external connection.

18. The MCP of claim 15, wherein the protective layer is permanently attached to the bottom of the lowest semiconductor chip.

19. The MCP of claim 15, wherein the protective layer comprises polyimide.

20. The MCP of claim 15, wherein each of the semiconductor chips is back lapped to reduce a total thickness of the MCP by thinning the bottom of each of the semiconductor chips.