TMR/GMR amplifier with input current compensation

• US 7,532,427 B1
• Filed: 01/11/2007
• Issued: 05/12/2009
• Est. Priority Date: 08/30/2004
• Status: Active Grant

• Current Assignee: Marvell Asia Pte Limited (Marvell Technology Group Limited)
• Original Assignee: Marvell International Limited (Marvell Technology Group Limited)
• Inventors: Voo, Thart Fah
• Primary Examiner(s): Feild; Joseph H
• Assistant Examiner(s): NEGRON, DANIELL L
• Application Number:
  US11/652,701
• Time in Patent Office: 852 Days
• Field of Search: None
• US Class Current: 360/67
• CPC Class Codes: G11B 2005/0018 by current biasing control or regulation
• CPC Class Codes: G11B 5/02 Recording, reproducing, or erasing methods; Read, write or erase circuits therefor
• CPC Class Codes: H03F 1/342 in field-effect transistor amplifiers
• CPC Class Codes: H03F 2200/144 the feedback circuit of the amplifier stage comprising a passive resistor and passive capacitor
• CPC Class Codes: H03F 2200/453 Controlling being realised by adding a replica circuit or by using one among multiple identical circuits as a replica circuit
• CPC Class Codes: H03F 2200/474 A current mirror being used as sensor
• CPC Class Codes: H03F 2203/45136 One differential amplifier in IC-block form being shown
• CPC Class Codes: H03F 2203/45528 the FBC comprising one or more passive resistors and being coupled between the LC and the IC
• CPC Class Codes: H03F 3/45475 using IC blocks as the active amplifying circuit

Abstract

An amplifier system with feedback current cancellation comprises an amplifier with at least one stage, a feedback network, first and second replica circuits, a buffer, second and third resistances, an operational amplifier (op-amp), a transistor, and a current mirror. The feedback network includes a first resistance that communicates with an input and an output of the amplifier. The first and second replica circuits approximately replicate DC characteristics of the output and the input of the amplifier, respectively. An output of the op-amp communicates with a control terminal of the transistor. The current mirror provides a current at the input of the amplifier that is proportional to a second current flowing through the transistor. The buffer communicates with the first replica circuit. The second resistance communicates with an output of the buffer. The third resistance communicates with the second resistance and with the second replica circuit.

Claims

1. An amplifier system with feedback current cancellation, comprising:

an amplifier that includes an input, an output, and at least one stage;

a feedback network that includes a first resistance having a first end that communicates with the input of the amplifier and an opposite end that communicates with the output of the amplifier;

first and second replica circuits that approximately replicate DC characteristics of the output and the input of the amplifier, respectively;

a buffer that includes an input that communicates with the first replica circuit and an output;

a second resistance that includes a first end that communicates with the output of the buffer and an opposite end;

a third resistance that includes a first end that communicates with the opposite end of the second resistance and an opposite end that communicates with the second replica circuit;

an operational amplifier (op-amp) that includes a first input that communicates with the first end of the third resistance, a second input that communicates with the opposite end of the third resistance, and an output;

a transistor that includes a control terminal that communicates with the output of the op-amp and a first terminal that communicates with the opposite end of the second resistance; and

a first current mirror that provides a first current at the input of the amplifier that is proportional to a second current flowing through the transistor.

2. The amplifier system of claim 1 wherein the second resistance has a resistance value that is approximately equal to a resistance value of the first resistance, and wherein the first current is approximately equal to the second current.

3. The amplifier system of claim 1 wherein the first and second replica circuits, the buffer, and the op-amp operate on standby power when power to the amplifier is turned off.

4. A sensor system comprising the amplifier system of claim 1 and further comprising:

a first current source; and

a variable resistance that communicates with, and is biased by, the first current source, wherein the input of the amplifier communicates with one end of the variable resistance.

5. A hard disk drive system comprising the sensor system of claim 4.

6. The sensor system of claim 4 wherein the second replica circuit comprises:

a second current source that provides current that is proportional to current provided by the first current source; and

a fourth resistance that communicates with, and is biased by, the second current source, and that has a resistance value that is proportional to a nominal resistance value of the variable resistance.

7. The amplifier system of claim 1 further comprising a second current mirror that provides a third current at the output of the amplifier that is approximately equal to the first current.

8. A sensor system comprising the amplifier system of claim 7 and further comprising:

a first current source; and

a variable resistance that communicates with, and is biased by, the first current source, wherein the input of the amplifier communicates with one end of the variable resistance.

9. A hard disk drive system comprising the sensor system of claim 8.

10. The amplifier system of claim 1 wherein the amplifier is arranged in a differential mode.

11. The amplifier system of claim 1 wherein the amplifier is arranged in a single-ended mode.

12. The amplifier system of claim 1 further comprising a DC blocking capacitance that communicates with the input of the amplifier.