Flash EEPROM system with simultaneous multiple data sector programming and storage of physical block characteristics in other designated blocks

• US 7,532,511 B2
• Filed: 04/02/2008
• Issued: 05/12/2009
• Est. Priority Date: 02/17/2000
• Status: Expired due to Fees

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk Corporation (Western Digital Corporation)
• Inventors: Conley, Kevin M., Mangan, John S., Craig, Jeffrey G.
• Primary Examiner(s): Nguyen; Tuan T.
• Application Number:
  US12/061,020
• Publication Number:
  US 20080192546A1
• Time in Patent Office: 405 Days
• Field of Search: 365/185.11, 365/185.09, 365/189.04, 365/185.29, 365/200
• US Class Current: 365/185.11
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 2212/7203 Temporary buffering, e.g. using volatile buffer or dedicated buffer blocks
• CPC Class Codes: G06F 2212/7207 management of metadata or control data
• CPC Class Codes: G06F 2212/7208 Multiple device management, e.g. distributing data over multiple flash devices
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/107 Programming all cells in an array, sector or block to the same state prior to flash erasing
• CPC Class Codes: G11C 16/3459 Circuits or methods to verify correct programming of nonvolatile memory cells
• CPC Class Codes: G11C 2216/14 Circuits or methods to write a page or sector of information simultaneously into a nonvolatile memory, typically a complete row or word line in flash memory
• CPC Class Codes: G11C 29/82 for EEPROMs

Abstract

A non-volatile memory system is formed of floating gate memory cells arranged in blocks as the smallest unit of memory cells that are erasable together. The system includes a number of features that may be implemented individually or in various cooperative combinations. One feature is the storage in separate blocks of the characteristics of a large number of blocks of cells in which user data is stored. These characteristics for user data blocks being accessed may, during operation of the memory system by its controller, be stored in a random access memory for ease of access and updating. According to another feature, multiple sectors of user data are stored at one time by alternately streaming chunks of data from the sectors to multiple memory blocks. Bytes of data in the stream may be shifted to avoid defective locations in the memory such as bad columns. Error correction codes may also be generated from the streaming data with a single generation circuit for the multiple sectors of data. The stream of data may further be transformed in order to tend to even out the wear among the blocks of memory. Yet another feature, for memory systems having multiple memory integrated circuit chips, provides a single system record that includes the capacity of each of the chips and assigned contiguous logical address ranges of user data blocks within the chips which the memory controller accesses when addressing a block, making it easier to manufacture a memory system with memory chips having different capacities. A typical form of the memory system is as a card that is removably connectable with a host system but may alternatively be implemented in a memory embedded in a host system. The memory cells may be operated with multiple states in order to store more than one bit of data per cell.

Claims

1. A method of operating a re-programmable non-volatile memory system having an array of memory cells organized into distinct blocks that individually include a number of simultaneously erasable memory cells capable of storing a particular quantity of data, the distinct memory cell blocks being further organized into a plurality of sub-arrays, comprising:

receiving and temporarily storing in a buffer memory at least a given number of sectors of user data to be programmed into the memory system,

moving data from one of the given number of sectors of user data in the buffer at a time to a respective one of a plurality of storage registers at a time, wherein moving data additionally comprises generating a redundancy code from the user data of the individual sectors and adding the generated code to the user data from which they are generated, and

thereafter moving the user data and the redundancy codes generated therefrom from the plurality of storage registers in parallel to respective ones of a plurality of memory cell blocks that are located within different ones of the plurality of sub-arrays.

2. The method according to claim 1, wherein moving the data additionally comprises moving the data through a dedicated electronic circuit provided as part of the memory system for generating the redundancy code.

3. The method according to claim 1, wherein generating the redundancy code comprises:

separately storing intermediate results of a redundancy code calculation for the individual sectors of data, and

combining the stored intermediate results with additional results of the redundancy code calculation for the same individual sectors.

4. The method according to claim 1, wherein moving the user data and the redundancy codes to the plurality of memory cell blocks comprises moving said user data and redundancy codes to the plurality of memory cell blocks within the plurality of sub-arrays that are located on a common integrated circuit.

5. The method according to claim 1, wherein the user data and the redundancy codes generated therefrom are moved into the plurality of memory cell blocks without data of information related to physical characteristics of the plurality of memory cell blocks or their operation.

6. The method according to claim 1, additionally comprising storing, in one or more of the distinct memory cell blocks other than the plurality of memory cell blocks, data of information related to physical characteristics of the plurality of memory cell blocks or their operation.

7. The method according to claim 6, wherein storing data of information related to physical characteristics of the plurality of memory cell blocks or their operation comprises storing an indication of whether any of the plurality of memory cell blocks is defective.

8. The method of claim 7, wherein, if any of the plurality of memory cell blocks is defective, storing data of information related to the physical characteristics of the plurality of memory cell blocks or their operation additionally comprises storing an address of another of the distinct memory cell blocks as a substitute for the defective memory cell block.

9. The method according to claim 7, wherein storing data of information related to physical characteristics of the plurality of memory cell blocks or their operation comprises storing data of usage characteristics of the plurality of memory cell blocks.

10. The method according to claim 6, wherein storing data of information related to physical characteristics of the plurality of memory cell blocks or their operation comprises storing data of any of programming, reading, erase or wear characteristics of the plurality of memory cell blocks.

11. The method according to claim 6, wherein the memory cells within the plurality of memory cell blocks are individually operated with more than two storage states in order to store more than one bit of data per memory cell, and wherein the memory cells within the one or more of the distinct memory cell blocks other than the plurality of memory cell blocks are individually operated with exactly two storage states in order to store exactly one bit of data per memory cell.

12. The method according to any one of claims 1-10, wherein the memory cells within at least the plurality of memory cell blocks are individually operated with more than two storage states in order to store more than one bit of data per memory cell.

13. The method according to any one of claims 1-11, wherein the memory system in which the method of operation is carried out is enclosed in a portable memory card having electrical contacts thereon accessible from outside the memory card for removably engaging mating contacts of a connector through which the user data are received.

14. A method of operating a memory system having a plurality of re-programmable non-volatile memory cells organized into distinct blocks of memory cells that are simultaneously erasable, comprising:

designating a first group of said blocks for storing user data and a second group of said blocks for storing information of physical characteristics of said first group of blocks or their operation,

storing, in individual ones of the first group of said blocks, user data plus information of at least one characteristic of the user data being stored therein, by simultaneously writing the user data plus information of said at least one characteristic of the user data into a plurality of blocks in the first group of blocks until at least a different sector of the user data plus the information of said at least one characteristic of the different sector of user data are written into each of the plurality of blocks in the first group, and

storing, in individual ones of the second group of said blocks, information of physical characteristics of the first group of blocks or their operation that does not include either user data or information of said at least one characteristic of the user data.

15. The method of claim 14, wherein the information of said at least one characteristic of the user data that is stored along with sectors of data includes redundancy codes that have been generated from the user data while the user data is being transferred to the plurality of the first group of blocks, individual ones of the redundancy codes being added to the user data from which they are generated.

16. The method of claim 15, wherein the redundancy codes are generated in a dedicated electronic circuit provided as part of the memory system for all of the plurality of the first group of blocks to which sectors of user data and redundancy codes generated therefrom are simultaneously being transferred.

17. The method of claim 14, wherein the information of said at least one characteristic of the user data that is stored along with sectors of data includes one or more bits that indicate any transformation of the user data within the data sector before being stored.

18. The method according to claim 14, wherein storing information of physical characteristics of the first group of blocks or their operation comprises storing an indication of whether any of the first group of blocks is defective.

19. The method according to claim 18, wherein, if any of the plurality of memory cell blocks is defective, storing data of information of physical characteristics of the first group of blocks or their operation additionally comprises storing an address of another of the blocks as a substitute for the defective block.

20. The method according to claim 18, wherein storing information of physical characteristics of the first group of blocks or their operation comprises storing data of usage characteristics of the first group of blocks.

21. The method according to claim 14, wherein storing information of physical characteristics of the first group of blocks or their operation comprises storing data of any of programming, reading, erase or wear characteristics of the first group of blocks.

22. The method according to any one of claims 14-21, wherein the memory cells within the first group of blocks are individually operated with more than two storage states in order to store more than one bit of data per memory cell, and the memory cells within the second group of blocks are individually operated with exactly two storage states in order to store exactly one bit of data per memory cell.

23. The method according to any one of claims 14-21, wherein the memory cells within at least the first group of blocks are individually operated with more than two storage states in order to store more than one bit of data per memory cell.

24. The method according to any one of claims 14-21, wherein the memory system in which the method of operation is carried out is enclosed in a portable memory card having electrical contacts thereon accessible from outside the memory card for removably engaging mating contacts of a connector through which the user data are received.