Bitline exclusion in verification operation

• US 7,532,524 B2
• Filed: 08/21/2007
• Issued: 05/12/2009
• Est. Priority Date: 06/15/2005
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Louie, Benjamin, Yip, Aaron, Hartono, Hendrik
• Primary Examiner(s): NGUYEN, TAN
• Application Number:
  US11/842,531
• Publication Number:
  US 20070285988A1
• Time in Patent Office: 630 Days
• Field of Search: 365/195
• US Class Current: 365/195
• CPC Class Codes: G11C 16/3454 Arrangements for verifying correct programming or for detecting overprogrammed cells
• CPC Class Codes: G11C 29/83 with reduced power consumption
• CPC Class Codes: G11C 29/832 with disconnection of faulty elements

Abstract

Methods and apparatuses for disabling a bad bitline for verification operations, and for determining whether a programming operation have failed, include setting a bitline disable latch for a bad bitline, and inhibiting operation of a program latch if the bitlines is excluded or if a programming operation fails.

Claims

1. A memory device, comprising:

an array of memory cells;

control circuitry to read, write and erase the memory cells;

address circuitry to latch address signals provided on address input connections; and

a circuit to exclude a bad bitline from memory operations and to detect a failed program sequence on a bitline for each of a plurality of bitlines in the memory, wherein the circuit further comprises;

a program verify circuit comprising;

first, second, and third transistors connected in series between a charged node and a ground potential, the first transistor gate connected to a verification enable signal, the second transistor gate connected to a program latch output signal, and the third transistor gate connected to a bitline disable latch signal, wherein the node is discharged to ground.

2. A memory device, comprising:

an array of memory cells;

control circuitry to read, write and erase the memory cells;

address circuitry to latch address signals provided on address input connections; and

a circuit to exclude a bad bitline from memory operations and to detect a failed program sequence on a bitline for each of a plurality of bitlines in the memory, wherein the circuit further comprises;

a read/verify sense circuit comprising;

a sense precharge transistor source to drain connected between a supply voltage and a sense node;

a bitline sense transistor source to drain connected between the sense node and a bitline; and

a transistor gate connected to the sense node, to inhibit operation of a program latch on sensing if a sensed bit on the bitline is programmed.

3. A memory device, comprising:

an array of memory cells;

control circuitry to read, write and erase the memory cells;

address circuitry to latch address signals provided on address input connections; and

a circuit to exclude a bad bitline from memory operations and to detect a failed program sequence on a bitline for each of a plurality of bitlines in the memory, wherein the circuit further comprises;

a bitline disable circuit comprising;

a bitline disable latch having an input and an output;

a program latch having an input and an output; and

a first transistor having a gate connected to the output of the bitline disable latch and source to drain connected between the output of the program latch and a ground potential;

a program verify circuit comprising;

second, third, and fourth transistors connected in series between a charged node and a ground potential, the second transistor gate connected to a verification enable signal, the third transistor gate connected to the program latch output signal, and the fourth transistor gate connected to the bitline disable latch input signal; and

a read/verify sense circuit comprising;

a sense precharge transistor source to drain connected between a supply voltage and a sense node;

a bitline sense transistor source to drain connected between the sense node and a bitline; and

a transistor gate connected to the sense node, to inhibit operation of the program latch on sensing if a sensed bit on the bitline is programmed.

4. The memory device of claim 3, wherein the memory device is a NAND memory device.

5. The memory device of claim 3, wherein the memory device is a flash memory device.

6. The memory device of claim 3, wherein the memory device is a non-volatile memory device.

7. A non-volatile memory device, comprising:

an array of floating gate memory cells;

control circuitry to read, write and erase the floating gate memory cells; and

address circuitry to latch address signals provided on address input connections; and

a circuit to exclude a bad bitline from memory operations and to detect a failed program sequence on a bitline for each of a plurality of bitlines in the memory, wherein the non-volatile memory device further comprises;

a program verify circuit comprising;

first, second, and third transistors connected in series between a charged node and a ground potential, the first transistor gate connected to a verification enable signal, the second transistor gate connected to a program latch output signal, and the third transistor gate connected to a bitline disable latch signal, wherein the node is discharged to ground.

8. The memory device of claim 7, wherein the memory device is a NAND memory device.

9. The memory device of claim 7, wherein the memory device is a flash memory device.

10. A non-volatile memory device, comprising:

an array of floating gate memory cells;

control circuitry to read, write and erase the floating gate memory cells; and

address circuitry to latch address signals provided on address input connections; and

a circuit to exclude a bad bitline from memory operations and to detect a failed program sequence on a bitline for each of a plurality of bitlines in the memory, wherein the non-volatile memory device further comprises;

a read/verify sense circuit comprising;

a sense precharge transistor source to drain connected between a supply voltage and a sense node;

a bitline sense transistor source to drain connected between the sense node and a bitline; and

a transistor gate connected to the sense node, to inhibit operation of a program latch on sensing if a sensed bit on the bitline is programmed.

11. A non-volatile memory device, comprising:

an array of floating gate memory cells;

control circuitry to read, write and erase the floating gate memory cells; and

address circuitry to latch address signals provided on address input connections; and

a circuit to exclude a bad bitline from memory operations and to detect a failed program sequence on a bitline for each of a plurality of bitlines in the memory, wherein the non-volatile memory device further comprises;

a bitline disable circuit comprising;

a bitline disable latch having an input and an output;

a program latch having an input and an output; and

a first transistor having a gate connected to the output of the bitline disable latch and source to drain connected between the output of the program latch and a ground potential;

a program verify circuit comprising;

second, third, and fourth transistors connected in series between a charged node and a ground potential, the second transistor gate connected to a verification enable signal, the third transistor gate connected to the program latch output signal, and the fourth transistor gate connected to the bitline disable latch input signal; and

a read/verify sense circuit comprising;

a sense precharge transistor source to drain connected between a supply voltage and a sense node;

a bitline sense transistor source to drain connected between the sense node and a bitline; and

a transistor gate connected to the sense node, to inhibit operation of the program latch on sensing if a sensed bit on the bitline is programmed.

12. A processing system, comprising:

a processor; and

a memory device coupled to the processor to store data provided by the processor and to provide data to the processor, the memory comprising;

an array of memory cells;

control circuitry to read, write and erase the memory cells;

address circuitry to latch address signals provided on address input connections; and

a circuit to exclude a bad bitline from memory operations and to detect a failed program sequence on a bitline for each of a plurality of bitlines in the memory, wherein the circuit further comprises;

a program verify circuit comprising;

first, second, and third transistors connected in series between a charged node and a ground potential, the first transistor gate connected to a verification enable signal, the second transistor gate connected to a program latch output signal, and the third transistor gate connected to a bitline disable latch signal, wherein the node is discharged to ground.

13. A processing system, comprising:

a processor; and

a memory device coupled to the processor to store data provided by the processor and to provide data to the processor, the memory comprising;

an array of memory cells;

control circuitry to read, write and erase the memory cells;

address circuitry to latch address signals provided on address input connections; and

a circuit to exclude a bad bitline from memory operations and to detect a failed program sequence on a bitline for each of a plurality of bitlines in the memory, wherein the circuit further comprises;

a read/verify sense circuit comprising;

a sense precharge transistor source to drain connected between a supply voltage and a sense node;

a bitline sense transistor source to drain connected between the sense node and a bitline; and

a transistor gate connected to the sense node, to inhibit operation of a program latch on sensing if a sensed bit on the bitline is programmed.

14. The system of claim 13, wherein the memory device is a NAND memory device.

15. A processing system, comprising:

a processor; and

a memory device coupled to the processor to store data provided by the processor and to provide data to the processor, the memory comprising;

an array of memory cells;

control circuitry to read, write and erase the memory cells;

address circuitry to latch address signals provided on address input connections; and

a circuit to exclude a bad bitline from memory operations and to detect a failed program sequence on a bitline for each of a plurality of bitlines in the memory, wherein the circuit further comprises;

a bitline disable circuit comprising;

a bitline disable latch having an input and an output;

a program latch having an input and an output; and

a first transistor having a gate connected to the output of the bitline disable latch and source to drain connected between the output of the program latch and a ground potential;

a program verify circuit comprising;

second, third, and fourth transistors connected in series between a charged node and a ground potential, the second transistor gate connected to a verification enable signal, the third transistor gate connected to the program latch output signal, and the fourth transistor gate connected to the bitline disable latch input signal; and

a read/verify sense circuit comprising;

a sense precharge transistor source to drain connected between a supply voltage and a sense node;

a bitline sense transistor source to drain connected between the sense node and a bitline; and

a transistor gate connected to the sense node, to inhibit operation of the program latch on sensing if a sensed bit on the bitline is programmed.

16. A flash memory device, comprising:

an array of floating gate memory cells;

control circuitry to read, write and erase the floating gate memory cells; and

address circuitry to latch address signals provided on address input connections; and

a circuit to exclude a bad bitline from memory operations and to detect a failed program sequence on a bitline for each of a plurality of bitlines in the memory, wherein the non-volatile memory device further comprises;

a program verify circuit comprising;

first, second, and third transistors connected in series between a charged node and a ground potential, the first transistor gate connected to a verification enable signal, the second transistor gate connected to a program latch output signal, and the third transistor gate connected to a bitline disable latch signal, wherein the node is discharged to ground.

17. A flash memory device, comprising:

an array of floating gate memory cells;

control circuitry to read, write and erase the floating gate memory cells; and

address circuitry to latch address signals provided on address input connections; and

a circuit to exclude a bad bitline from memory operations and to detect a failed program sequence on a bitline for each of a plurality of bitlines in the memory, wherein the non-volatile memory device further comprises;

a read/verify sense circuit comprising;

a sense precharge transistor source to drain connected between a supply voltage and a sense node;

a bitline sense transistor source to drain connected between the sense node and a bitline; and

a transistor gate connected to the sense node, to inhibit operation of a program latch on sensing if a sensed bit on the bitline is programmed.

18. A flash memory device, comprising:

an array of floating gate memory cells;

control circuitry to read, write and erase the floating gate memory cells; and

address circuitry to latch address signals provided on address input connections; and

a circuit to exclude a bad bitline from memory operations and to detect a failed program sequence on a bitline for each of a plurality of bitlines in the memory, wherein the non-volatile memory device further comprises;

a bitline disable circuit comprising;

a bitline disable latch having an input and an output;

a program latch having an input and an output; and

a first transistor having a gate connected to the output of the bitline disable latch and source to drain connected between the output of the program latch and a ground potential;

a program verify circuit comprising;

second, third, and fourth transistors connected in series between a charged node and a ground potential, the second transistor gate connected to a verification enable signal, the third transistor gate connected to the program latch output signal, and the fourth transistor gate connected to the bitline disable latch input signal; and

a read/verify sense circuit comprising;

a sense precharge transistor source to drain connected between a supply voltage and a sense node;

a bitline sense transistor source to drain connected between the sense node and a bitline; and

a transistor gate connected to the sense node, to inhibit operation of the program latch on sensing if a sensed bit on the bitline is programmed.