Memory module with a circuit providing load isolation and memory domain translation

• US 7,532,537 B2
• Filed: 01/19/2006
• Issued: 05/12/2009
• Est. Priority Date: 03/05/2004
• Status: Active Grant

• Current Assignee: Netlist, Inc.
• Original Assignee: Netlist, Inc.
• Inventors: Solomon, Jeffrey C., Bhakta, Jayesh R.
• Primary Examiner(s): Nguyen; Van Thu
• Assistant Examiner(s): Sofocleous; Alexander
• Application Number:
  US11/335,875
• Publication Number:
  US 20060262586A1
• Time in Patent Office: 1,209 Days
• Field of Search: 365/51, 365/52, 365/191, 365/230.03, 365/230.06, 365/230.08, 365/233.1, 365/233.13
• US Class Current: 365/230.06
• CPC Class Codes: G06F 12/0207 with multidimensional access, e.g. row/column, matrix
• CPC Class Codes: G06F 12/0215 with look ahead addressing means
• CPC Class Codes: G11C 2207/105 Aspects related to pads, pins or terminals
• CPC Class Codes: G11C 5/04 Supports for storage elements , e.g. memory modules; Mounting or fixing of storage elements on such supports
• CPC Class Codes: G11C 5/066 Means for reducing external access-lines for a semiconductor memory clip, e.g. by multiplexing at least address and data signals
• CPC Class Codes: G11C 7/1048 Data bus control circuits, e.g. precharging, presetting, equalising
• CPC Class Codes: G11C 8/12 Group selection circuits, e.g. for memory block selection, chip selection, array selection
• CPC Class Codes: H05K 1/181 associated with surface mounted components
• CPC Class Codes: H05K 2201/10159 Memory
• CPC Class Codes: H05K 2203/1572 Processing both sides of a PCB by the same process; Providing a similar arrangement of components on both sides; Making interlayer connections from two sides
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management
• CPC Class Codes: Y02P 70/50 Manufacturing or production processes characterised by the final manufactured product

Abstract

A memory module includes a plurality of memory devices and a circuit. Each memory device has a corresponding load. The circuit is electrically coupled to the plurality of memory devices and is configured to be electrically coupled to a memory controller of a computer system. The circuit selectively isolates one or more of the loads of the memory devices from the computer system. The circuit comprises logic which translates between a system memory domain of the computer system and a physical memory domain of the memory module.

Claims

1. A memory module comprising:

a plurality of memory devices, each memory device having a corresponding load; and

a circuit electrically coupled to the plurality of memory devices and configured to be electrically coupled to a memory controller of a computer system, the circuit selectively isolating one or more of the loads of the memory devices from the computer system, the circuit comprising logic which translates between a system memory domain of the computer system and a physical memory domain of the memory module, wherein the system memory domain is compatible with a first number of chip selects, and the physical memory domain is compatible with a second number of chip selects equal to twice the first number of chip selects.

2. The memory module of claim 1, wherein the circuit comprises a logic element selected from a group consisting of:

a programmable-logic device (PLD), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), a custom-designed semiconductor device, and a complex programmable-logic device (CPLD).

3. The memory module of claim 2, wherein the circuit further comprises one or more switches operatively coupled to the logic element to receive control signals from the logic element.

4. The memory module of claim 1, wherein the plurality of memory devices has a first number of memory devices, and the circuit selectively isolates the loads of a second number of the memory devices from the computer system, the second number less than the first number.

5. The memory module of claim 4, wherein the first number of memory devices are configured in a plurality of ranks, and wherein the second number of memory devices are configured as one rank of the plurality of ranks.

6. The memory module of claim 1, wherein the logic translates address signals in the system memory domain to address signals in the physical memory domain.

7. The memory module of claim 1, wherein the plurality of memory devices are arranged in one or more ranks and the system memory domain is compatible to a first memory density per rank, and the physical memory domain is compatible with a second memory density per rank equal to twice the first memory density per rank.

8. The memory module of claim 1, wherein the plurality of memory devices comprises a pair of memory devices, each memory device of the pair having a first memory capacity, the pair of memory devices configured to simulate a memory device having a second memory capacity equal to twice the first memory capacity.

9. The memory module of claim 1, wherein the memory module comprises a dual inline memory module.

10. The memory module of claim 9, wherein the memory module comprises a rank-buffered dual inline memory module.

11. The memory module of claim 1, wherein the memory module comprises a DDR2 SDRAM memory array.

12. The memory module of claim 1, wherein the circuit selectively isolates the loads of the memory devices from the computer system in response to a command or address signal received from the computer system.

13. A method of using a memory module with a computer system, the method comprising:

providing a memory module having a plurality of memory devices and a circuit electrically coupled to the plurality of memory devices, the circuit configured to be electrically coupled to a computer system, each memory device having a corresponding load;

electrically coupling the memory module to the computer system; and

activating the circuit to selectively isolate at least one of the loads of the memory devices from the computer system and to translate between a system memory domain of the computer system and a physical memory domain of the memory module, wherein the system memory domain is compatible with a first number of chip selects, and the physical memory domain is compatible with a second number of chip selects equal to twice the first number of chip selects.

14. The method of claim 13, wherein the plurality of memory devices comprises a pair of memory devices, each memory device of the pair having a first memory capacity, the pair of memory devices configured to simulate a memory device having a second memory capacity equal to twice the first memory capacity.

15. The method of claim 13, wherein the logic translates address signals in the system memory domain to address signals in the physical memory domain.

16. The method of claim 13, wherein the plurality of memory devices are arranged in one or more ranks and the system memory domain is compatible to a first memory density per rank, and the physical memory domain is compatible with a second memory density per rank equal to twice the first memory density per rank.

17. The method of claim 13, wherein the memory module comprises a dual inline memory module.

18. A memory module connectable to a computer system, the memory module comprising:

a first memory device having a first data signal line and a first data strobe signal line;

a second memory device having a second data signal line and a second data strobe signal line;

a common data signal line connectable to the computer system; and

a device electrically coupled to the first data signal line, to the second data signal line, and to the common data signal line, the device selectively electrically coupling the first data signal line to the common data signal line and selectively electrically coupling the second data signal line to the common data signal line, the device comprising logic which translates between a system memory domain of the computer system and a physical memory domain of the memory module, wherein the system memory domain is compatible with a first number of chip selects, and the physical memory domain is compatible with a second number of chip selects equal to twice the first, number of chip selects.

19. The memory module of claim 18, wherein the device comprises a logic element.

20. The memory module of claim 19, wherein the logic element is selected from the group consisting of:

an application-specific integrated circuit, a custom-programmable logic device, and a field-programmable gate array.

21. The memory module of claim 18, wherein the device selectively electrically couples the first data signal line to the common data signal line and selectively electrically couples the second data signal line to the common data signal line.

22. The memory module of claim 18, wherein the memory module further comprises a common data strobe signal line connectable to the computer system, the device electrically coupled to the first data strobe signal line, to the second data strobe signal line, and to the common data strobe signal line, the device selectively electrically coupling the first data strobe signal line to the common data strobe signal line and selectively electrically coupling the second data strobe signal line to the common data strobe signal line.

23. The memory module of claim 22, wherein the device selectively electrically couples the first data strobe signal line to the common data strobe signal line and selectively electrically couples the second data strobe signal line to the common data strobe signal line.

24. A memory module comprising:

a plurality of memory devices arranged in one or more ranks, each memory device having a corresponding load; and

a circuit electrically coupled to the plurality of memory devices and configured to be electrically coupled to a memory controller of a computer system, the circuit selectively isolating one or more of the loads of the memory devices from the computer system, the circuit comprising logic which translates between a system memory domain of the computer system and a physical memory domain of the memory module, wherein the system memory domain is compatible to a first memory density per rank, and the physical memory domain is compatible with a second memory density per rank equal to twice the first memory density per rank.

25. The memory module of claim 24, wherein the circuit comprises a logic element selected from a group consisting of:

a programmable-logic device (PLD), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), a custom-designed semiconductor device, and a complex programmable-logic device (CPLD).

26. The memory module of claim 25, wherein the circuit further comprises one or more switches operatively coupled to the logic element to receive control signals from the logic element.

27. The memory module of claim 24, wherein the plurality of memory devices has a first number of memory devices, and the circuit selectively isolates the loads of a second number of the memory devices from the computer system, the second number less than the first number.

28. The memory module of claim 27, wherein the first number of memory devices are configured in a plurality of ranks, and wherein the second number of memory devices are configured as one rank of the plurality of ranks.

29. The memory module of claim 24, wherein the logic translates address signals in the system memory domain to address signals in the physical memory domain.

30. The memory module of claim 24, wherein the plurality of memory devices comprises a pair of memory devices, each memory device of the pair having a first memory capacity, the pair of memory devices configured to simulate a memory device having a second memory capacity equal to twice the first memory capacity.

31. The memory module of claim 24, wherein the memory module comprises a dual inline memory module.

32. The memory module of claim 31, wherein the memory module comprises a rank-buffered dual inline memory module.

33. The memory module of claim 24, wherein the memory module comprises a DDR2 SDRAM memory array.

34. The memory module of claim 24, wherein the circuit selectively isolates the loads of the memory devices from the computer system in response to a command or address signal received from the computer system.

35. A method of using a memory module with a computer system, the method comprising:

providing a memory module having a plurality of memory devices arranged in one or more ranks and a circuit electrically coupled to the plurality of memory devices, the circuit configured to be electrically coupled to a computer system, each memory device having a corresponding load;

electrically coupling the memory module to the computer system; and

activating the circuit to selectively isolate at least one of the loads of the memory devices from the computer system and to translate between a system memory domain of the computer system and a physical memory domain of the memory module, wherein the system memory domain is compatible to a first memory density per rank, and the physical memory domain is compatible with a second memory density per rank equal to twice the first memory density per rank.

36. The method of claim 35, wherein the plurality of memory devices comprises a pair of memory devices, each memory device of the pair having a first memory capacity, the pair of memory devices configured to simulate a memory device having a second memory capacity equal to twice the first memory capacity.

37. The method of claim 35, wherein the logic translates address signals in the system memory domain to address signals in the physical memory domain.

38. The method of claim 35, wherein the memory module comprises a dual inline memory module.

39. A memory module connectable to a computer system, the memory module comprising:

a first memory device having a first data signal line and a first data strobe signal line;

a second memory device having a second data signal line and a second data strobe signal line;

a common data signal line connectable to the computer system; and

a device electrically coupled to the first data signal line, to the second data signal line, and to the common data signal line, the device selectively electrically coupling the first data signal line to the common data signal line and selectively electrically coupling the second data signal line to the common data signal line, the device comprising logic which translates between a system memory domain of the computer system and a physical memory domain of the memory module, wherein the system memory domain is compatible to a first memory density per memory device, and the physical memory domain is compatible with a second memory density per memory device equal to twice the first memory density per memory device.

40. The memory module of claim 39, wherein the device comprises a logic element.

41. The memory module of claim 39, wherein the device selectively electrically couples the first data signal line to the common data signal line and selectively electrically couples the second data signal line to the common data signal line.

42. The memory module of claim 41, wherein the logic element is selected from the group consisting of:

an application-specific integrated circuit, a custom-programmable logic device, and a field-programmable gate array.

43. The memory module of claim 39, wherein the memory module further comprises a common data strobe signal line connectable to the computer system, the device electrically coupled to the first data strobe signal line, to the second data strobe signal line, and to the common data strobe signal line, the device selectively electrically coupling the first data strobe signal line to the common data strobe signal line and selectively electrically coupling the second data strobe signal line to the common data strobe signal line.

44. The memory module of claim 43, wherein the device selectively electrically couples the first data strobe signal line to the common data strobe signal line and selectively electrically couples the second data strobe signal line to the common data strobe signal line.