Automatic operand load, modify and store

• US 7,533,250 B2
• Filed: 07/25/2005
• Issued: 05/12/2009
• Est. Priority Date: 07/27/2004
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Cabillic, Gilbert, Chauvel, Gerard, Lesot, Jean-Philippe
• Primary Examiner(s): Coleman; Eric
• Assistant Examiner(s): Faherty; Corey S
• Application Number:
  US11/188,311
• Publication Number:
  US 20060026400A1
• Time in Patent Office: 1,387 Days
• Field of Search: 712/226
• US Class Current: 712/226
• CPC Class Codes: G06F 12/0802 Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
• CPC Class Codes: G06F 12/1081 for peripheral access to main memory, e.g. direct memory access [DMA]
• CPC Class Codes: G06F 2212/6012 of operating mode, e.g. cache mode or local memory mode
• CPC Class Codes: G06F 9/30174 for non-native instruction set, e.g. Javabyte, legacy code
• CPC Class Codes: G06F 9/45504 Abstract machines for programme code execution, e.g. Java virtual machine [JVM], interpreters, emulators
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A processor comprising a decode logic coupled to a first storage unit and comprising a data structure. The processor also comprises a second storage unit coupled to the decode logic. The decode logic obtains a single instruction from the first storage unit and, if indicated by a first bit in the data structure, processes a group of instructions in lieu of the single instruction, where the single instruction requires an operand. If indicated by a second bit in the data structure, the decode logic obtains the operand from the first storage unit, modifies the operand, and stores the operand to the second storage unit for use by the group of instructions.

Claims

1. A processor, comprising:

decode logic coupled to an instruction cache;

a micro-sequence vector table coupled to the decode logic, wherein the micro-sequence vector table comprises one entry for each bytecode in an instruction set of the processor, wherein all fields in an entry are unique to a bytecode corresponding to the entry; and

a storage unit coupled to the decode logic,

wherein the decode logic is configured to;

obtain a single bytecode from the instruction cache, wherein the single bytecode requires an immediate operand stored in the instruction cache,

use the single bytecode to locate the entry corresponding to the single bytecode in the micro-sequence vector table,

cause the processor to directly execute the single bytecode using the immediate operand when a first field in the entry indicates that the single bytecode is to be executed, and,

when the first field in the entry indicates that a micro-sequence is to be executed instead of the single bytecode and a second field in the entry indicates that the single bytecode requires the immediate operand, obtain the immediate operand from the instruction cache, modify the immediate operand when a third field in the entry indicates that the immediate operand is to be modified, and store the modified immediate operand in the storage unit for use by the micro-sequence.

2. The processor of claim 1, wherein the decode logic is further configured to modify the immediate operand by performing a sign extension on the immediate operand prior to storing the immediate operand in the storage unit.

3. The processor of claim 1, wherein the decode logic is further configured to modify the immediate operand by performing a zero extension on the immediate operand prior to storing the immediate operand in the storage unit.

4. The processor of claim 1, wherein the decode logic is further configured to modify the immediate operand by shifting the immediate operand left by two bits.

5. The processor of claim 1, wherein the decode logic is further configured to modify the immediate operand prior to storing the immediate operand in the storage unit.

6. The processor of claim 1, wherein a size of the immediate operand is indicated by bits in the second field.

7. The processor of claim 1, wherein a size of the immediate operand is selected from a group consisting of one byte, two bytes and four bytes.

8. The processor of claim 1, wherein the decode logic is further configured to obtain, modify, and store the immediate operand before the micro-sequence is executed.

9. An electronic device, comprising:

a first processor; and

a second processor coupled to the first processor, wherein the second processor is configured to directly execute a stack-based instruction set comprising bytecodes and a complementary instruction set comprising micro-sequence instructions, and wherein the second processor comprises;

an instruction cache configured to store bytecodes and micro-sequence instructions;

a register dedicated for storage of an immediate operand of a bytecode;

decode logic coupled to the instruction cache and the register; and

a micro-sequence vector table coupled to the decode logic, wherein the micro-sequence vector table comprises one entry for each bytecode of the stack-based instruction set, and wherein each entry comprises a plurality of fields unique to a bytecode corresponding to the entry, wherein the plurality of fields comprises;

a first field configured to indicate whether the corresponding bytecode is to be executed directly or a micro-sequence is to be executed rather than the corresponding bytecode;

a second field configured to indicate whether the corresponding bytecode requires an immediate operand stored in the instruction cache;

a third field configured to indicate whether the decode logic is to modify the immediate operand; and

a fourth field configured to store a reference to the micro-sequence,

wherein the decode logic is configured to;

obtain a bytecode from the instruction cache, wherein the bytecode requires an immediate operand stored in the instruction cache,

use the bytecode to locate the entry in the micro-sequence vector table corresponding to the bytecode,

cause the second processor to directly execute the single bytecode using the immediate operand when the first field of the entry indicates that the single bytecode is to be executed,

obtain the immediate operand for the bytecode from the instruction cache when the first field of the entry indicates that a micro-sequence is to be executed and the second field of the entry indicates that the bytecode requires the immediate operand,

modify the immediate operand when the third field indicates the immediate operand is to be modified, and

store the modified operand in the register for use by a micro-sequence referenced in the fourth field of the entry.

10. The electronic device of claim 9, wherein the third field is further configured to indicate that the decode logic is to perform a sign extension on the immediate operand.

11. The electronic device of claim 9, wherein the third field is further configured to indicate that the decode logic is to perform a zero extension on the immediate operand.

12. The electronic device of claim 9, wherein the third field is further configured to indicate that the decode logic is to shift the immediate operand.

13. The electronic device of claim 12, wherein the third field is further configured to indicate that the decode logic is to shift the immediate operand left by two bits.

14. The electronic device of claim 9, wherein the second field is further configured to indicate a size of the immediate operand.

15. The electronic device of claim 9, wherein the electronic device is selected from the group consisting of a battery-operated device and a wireless communication device.

16. A method, comprising:

fetching a single bytecode from an instruction cache, wherein the single bytecode requires an immediate operand stored in the instruction cache;

using the single bytecode to locate an entry corresponding to the single bytecode in a micro-sequence vector table, wherein the micro-sequence vector table comprises one entry for each bytecode in an instruction set of a processor, wherein all fields in an entry are unique to a bytecode corresponding to the entry;

causing the processor to directly execute the single bytecode using the immediate operand when a first field in the entry indicates that the single bytecode is to be executed; and

when the first field in the entry indicates that a micro-sequence is to be executed instead of the single bytecode and a second field in the entry indicates that the immediate operand is required by the single bytecode, obtaining the immediate operand from the instruction cache;

modifying the immediate operand when a third field in the entry indicates that the immediate operand is to be modified; and

storing the modified immediate operand in a register for use by the micro-sequence.

17. The method of claim 16, wherein a size of the immediate operand is indicated by a configuration of the second field in the entry.

18. The method of claim 16, wherein modifying the immediate operand further comprises performing at least one of a sign extension, a zero extension or a shift operation on the immediate operand.

19. The method of claim 16, wherein storing the immediate operand further comprises storing the immediate operand before the micro-sequence is executed.