Adaptive decoder for decoding an asynchronous data stream

• US 7,533,326 B2
• Filed: 12/06/2005
• Issued: 05/12/2009
• Est. Priority Date: 12/06/2005
• Status: Active Grant

• Current Assignee: Microchip Technology Incorporated
• Original Assignee: Micrel Incorporated (Microchip Technology Incorporated)
• Inventors: Chambers, Peter
• Primary Examiner(s): Abraham; Esaw T
• Assistant Examiner(s): Alphonse; Fritz
• Application Number:
  US11/295,318
• Publication Number:
  US 20070130497A1
• Time in Patent Office: 1,253 Days
• Field of Search: 714/780, 714/786, 714/789, 714/797, 714/781, 370/504, 370/316
• US Class Current: 714/780
• CPC Class Codes: H04L 1/0045 Arrangements at the receiver end
• CPC Class Codes: H04L 1/1829 Arrangements specially adapted for the receiver end

Abstract

A data decoder for decoding an asynchronous incoming data stream includes a bit engine receiving information describing the incoming data stream and generating a decoded data stream. In one embodiment, the bit engine includes a best-fit bit analysis block performing a pattern match operation for each data bit of the incoming data stream using the information describing the incoming data stream. The best-fit bit analysis block is operative to find a pattern of data bits that best matches the data bits in the incoming data stream. The bit engine further includes a missing bit insertion block to insert a dummy bit for each data bit where the best-fit bit analysis block cannot find a pattern match. An error correction block performs forward error correction on the decoded data stream, including the dummy bits, to generate a corrected outgoing data stream.

Claims

1. A data decoder for decoding an asynchronous incoming data stream, the data decoder comprising:

an incoming data processing block for receiving the incoming data stream and analyzing the incoming data stream to generate information describing the incoming data stream;

a bit engine receiving the information describing the incoming data stream and generating a decoded data stream, the bit engine comprising;

a best-fit bit analysis block performing a pattern match operation for each data bit of the incoming data stream using the information describing the incoming data stream, the best-fit bit analysis block operative to find a pattern of data bits that best matches the data bits in the incoming data stream; and

a missing bit insertion block to insert a dummy bit for each data bit where the best-fit bit analysis block cannot find a pattern match; and

an error correction block receiving the decoded data stream and performing forward error correction on the decoded data stream, the error correction block generating a corrected outgoing data stream having corrected data values.

2. The data decoder of claim 1, wherein the incoming data stream comprises an encoded data stream.

3. The data decoder of claim 2, wherein the incoming data stream comprises a data stream encoded using the Manchester coding scheme.

4. The data decoder of claim 3, wherein the incoming data processing block comprises an edge detect and integrator block for detecting and isolating the positive-going edges and the negative-going edges of the incoming data stream and also for measuring the duration of successive high/low transitions.

5. The data decoder of claim 4, wherein the incoming data processing block further comprises a pulse deglitch and reshape block for performing filtering functions on the incoming data stream.

6. The data decoder of claim 1, further comprising:

a dead bitstream timer for counting the number of dummy bits inserted consecutively by the missing bit insertion block, the dead bitstream timer asserting a signal when the number of dummy bits inserted consecutively reaches a predetermined limit, the signal operative to terminate the decoding of the incoming data stream and instruct the bit engine to reject the incoming data stream as invalid.

7. The data decoder of claim 6, wherein the predetermined limit of the dead bitstream timer comprises a number of corrupted data bits in a row exceeding the error correction capability of the error correction block.

8. The data decoder of claim 6, wherein the predetermined limit is 10 dummy bits.

9. The data decoder of claim 1, wherein the dummy bit has a data value of one or zero.

10. The data decoder of claim 1, further comprising:

a data register for storing the decoded data stream; and

a sync pattern detect block for detecting specific sequences of valid bits in the decoded data stream.

11. A method of decoding an asynchronous incoming data stream comprising:

receiving the incoming data stream;

analyzing the incoming data stream;

generating information describing the incoming data stream;

performing a pattern match for each data bit of the incoming data stream using the information describing the incoming data stream;

determining a pattern of data bits that best matches the data bits in the incoming data stream using best-fit bit analysis;

inserting a dummy bit for each data bit where the best-fit bit analysis cannot find a pattern match, thereby generating a decoded data stream; and

correcting errors in the decoded data stream using forward error correction routines to generate an outgoing data stream having corrected data values.

12. The method of claim 11, wherein the incoming data stream comprises an encoded data stream.

13. The method of claim 12, wherein the incoming data stream comprises a data stream encoded using the Manchester coding scheme.

14. The method of claim 13, wherein analyzing the incoming data stream comprises:

detecting and isolating the positive-going edges and the negative-going edges of the incoming data stream; and

measuring the duration of successive high/low transitions.

15. The method of claim 14, wherein analyzing the incoming data stream further comprises:

filtering the incoming data stream prior to detecting and isolating the positive-going edges and the negative-going edges of the incoming data stream.

16. The method of claim 11, further comprising:

counting the number of dummy bits inserted consecutively;

asserting a signal when the number of dummy bits inserted consecutively reaches a predetermined limit; and

terminating the decoding of the incoming data stream and rejecting the incoming data stream as invalid as a result of the signal being asserted.

17. The method of claim 16, wherein the predetermined limit of the dead bitstream timer comprises a number of corrupted data bits in a row exceeding the error correction capability of the error correction routines.

18. The method of claim 17, wherein the predetermined limit is 10 dummy bits.

19. The method of claim 11, wherein the dummy bit has a data value of one or zero.