Post passivation interconnection schemes on top of IC chips

• US 7,534,718 B2
• Filed: 10/30/2007
• Issued: 05/19/2009
• Est. Priority Date: 10/18/2000
• Status: Expired due to Fees

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Megica Corporation (Chipbond Technology Corporation)
• Inventors: Lin, Mou-Shiung, Lee, Jin-Yuan
• Primary Examiner(s): Ghyka; Alexander G
• Application Number:
  US11/927,721
• Publication Number:
  US 20080085597A1
• Time in Patent Office: 567 Days
• Field of Search: 438/623, 438/637
• US Class Current: 438/623
• CPC Class Codes: H01L 21/768 Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
• CPC Class Codes: H01L 21/76801 characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
• CPC Class Codes: H01L 21/76838 characterised by the formation and the after-treatment of the conductors etching for patterning the conductors H01L21/3213
• CPC Class Codes: H01L 23/5222 Capacitive arrangements or effects of, or between wiring layers other capacitive arrangements H01L23/642
• CPC Class Codes: H01L 23/5223 Capacitor integral with wiring layers
• CPC Class Codes: H01L 23/5227 Inductive arrangements or effects of, or between, wiring layers other inductive arrangements H01L23/645
• CPC Class Codes: H01L 23/5283 Cross-sectional geometry
• CPC Class Codes: H01L 23/5286 Arrangements of power or ground buses
• CPC Class Codes: H01L 23/5329 Insulating materials
• CPC Class Codes: H01L 23/53295 Stacked insulating layers
• CPC Class Codes: H01L 23/60 Protection against electrostatic charges or discharges, e.g. Faraday shields
• CPC Class Codes: H01L 23/62 Protection against overvoltage, e.g. fuses, shunts
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 27/0248 for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/12042 LASER
• CPC Class Codes: H01L 2924/12044 OLED
• CPC Class Codes: H01L 2924/14 Integrated circuits
• CPC Class Codes: H01L 2924/3011 Impedance

Abstract

A new method is provided for the creation of interconnect lines. Fine line interconnects are provided in a first layer of dielectric overlying semiconductor circuits that have been created in or on the surface of a substrate. A layer of passivation is deposited over the layer of dielectric, a thick second layer of dielectric is created over the surface of the layer of passivation. Thick and wide interconnect lines are created in the thick second layer of dielectric. The first layer of dielectric may also be eliminated, creating the wide thick interconnect network on the surface of the layer of passivation that has been deposited over the surface of a substrate.

Claims

1. A method for fabricating a chip, comprising:

providing a silicon substrate, multiple devices in and on said silicon substrate, a first dielectric layer over said silicon substrate, a first metallization structure over said first dielectric layer, wherein said first metallization structure is connected to said multiple devices, wherein said first metallization structure comprises a first metal layer and a second metal layer over said first metal layer, and wherein said first metallization structure comprises a first pad having a top surface with a first region and a second region between said first region and a sidewall of said first pad, a second dielectric layer between said first and second metal layers, a passivation layer over said first metallization structure, over said first and second dielectric layers and on said second region, wherein a first opening in said passivation layer is over said first region, wherein said first opening has a transverse dimension between 0.5 and 30 micrometers, and wherein said passivation layer comprises a topmost insulating nitride layer of said chip, and a polymer layer on said passivation layer, wherein a second opening in said polymer layer is over said first region, wherein said second opening has a transverse dimension between 0.5 and 30 micrometers, and wherein said polymer layer has a thickness between 2 and 150 micrometers and greater than that of said passivation layer; and

forming a second metallization structure in said second opening and over said polymer layer, wherein said forming said second metallization structure comprises forming a third metal layer, followed by forming a patterned photoresist layer, followed by electroplating a fourth metal layer, followed by removing said patterned photoresist layer, followed by etching said third metal layer.

2. The method of claim 1, wherein said forming said third metal layer comprises a sputtering process.

3. The method of claim 1, wherein said polymer layer comprises polyimide.

4. The method of claim 1, wherein said polymer layer comprises benzocyclobutene (BCB).

5. The method of claim 1, wherein said first metallization structure comprises an electroplated metal.

6. The method of claim 1, wherein said first metallization structure further comprises a second pad, wherein a third opening in said passivation layer is over said second pad, and a fourth opening in said polymer layer is over said second pad, wherein said forming said second metallization structure further comprises said forming said second metallization structure in said fourth opening.

7. The method of claim 1, wherein said forming said patterned photoresist layer comprises a coating process.

8. The method of claim 1, wherein said polymer layer is formed by a process comprising a spin-on coating process.

9. A method for fabricating a chip, comprising:

providing a silicon substrate, multiple devices in and on said silicon substrate, a first dielectric layer over said silicon substrate, a first metallization structure over said first dielectric layer, wherein said first metallization structure is connected to said multiple devices, wherein said first metallization structure comprises a first metal layer and a second metal layer over said first metal layer, wherein said first metallization structure comprises a first pad having a top surface with a first region and a second region between said first region and a sidewall of said first pad, and wherein said first metallization structure is formed by a process comprising a damascene process, an electroplating process and a CMP process, a second dielectric layer between said first and second metal layers, a passivation layer over said first metallization structure, over said first and second dielectric layers and on said second region, wherein a first opening in said passivation layer is over said first region, wherein said first opening has a transverse dimension between 0.5 and 30 micrometers, and wherein said passivation layer comprises a topmost insulating nitride layer of said chip, and a polymer layer on said passivation layer, wherein a second opening in said polymer layer is over said first region, wherein said second opening has a transverse dimension between 0.5 and 30 micrometers, and wherein said polymer layer has a thickness between 2 and 150 micrometers and greater than that of said passivation layer; and

forming a second metallization structure in said second opening and over said polymer layer, wherein said forming said second metallization structure comprises forming a third metal layer, followed by forming a patterned photoresist layer, followed by electroplating a fourth metal layer, followed by removing said patterned photoresist layer, followed by etching said third metal layer.

10. The method of claim 9, wherein said forming said third metal layer comprises a sputtering process.

11. The method of claim 9, wherein said polymer layer comprises polyimide.

12. The method of claim 9, wherein said polymer layer comprises benzocyclobutene (BCB).

13. The method of claim 9, wherein said first metallization structure further comprises a second pad, wherein a third opening in said passivation layer is over said second pad, and a fourth opening in said polymer layer is over said second pad, wherein said forming said second metallization structure further comprises said forming said second metallization structure in said fourth opening.

14. The method of claim 9, wherein said polymer layer is formed by a process comprising a spin-on coating process.

15. A method for fabricating a chip, comprising:

providing a silicon substrate, multiple devices in and on said silicon substrate, a first dielectric layer over said silicon substrate, a first metallization structure over said first dielectric layer, wherein said first metallization structure is connected to said multiple devices, wherein said first metallization structure comprises a first metal layer and a second metal layer over said first metal layer, wherein said first metallization structure comprises a first pad having a top surface with a first region and a second region between said first region and a sidewall of said first pad, wherein said first pad has a size between 0.5 and 30 micrometers, and wherein said first metallization structure is formed by a process comprising a damascene process, an electroplating process and a CMP process, a second dielectric layer between said first and second metal layers, a passivation layer over said first metallization structure, over said first and second dielectric layers and on said second region, wherein a first opening in said passivation layer is over said first region, wherein said first opening has a transverse dimension between 0.5 and 30 micrometers, and wherein said passivation layer comprises a topmost insulating nitride layer of said chip, and a polymer layer on said passivation layer, wherein a second opening in said polymer layer is over said first region, wherein said second opening has a transverse dimension between 0.5 and 30 micrometers, and wherein said polymer layer has a thickness between 2 and 150 micrometers and greater than that of said passivation layer; and

forming a second metallization structure in said second opening and over said polymer layer, wherein said forming said second metallization structure comprises forming a third metal layer, followed by forming a patterned photoresist layer, followed by electroplating a fourth metal layer, followed by removing said patterned photoresist layer, followed by etching said third metal layer.

16. The method of claim 15, wherein said forming said third metal layer comprises a sputtering process.

17. The method of claim 15, wherein said polymer layer comprises polyimide.

18. The method of claim 15, wherein said polymer layer comprises benzocyclobutene (BCB).

19. The method of claim 15, wherein said first metallization structure further comprises a second pad, wherein a third opening in said passivation layer is over said second pad, and a fourth opening in said polymer layer is over said second pad, wherein said forming said second metallization structure further comprises said forming said second metallization structure in said fourth opening.

20. The method of claim 15, wherein said polymer layer is formed by a process comprising a spin-on coating process.