DMOS transistor with a poly-filled deep trench for improved performance

• US 7,535,057 B2
• Filed: 09/23/2005
• Issued: 05/19/2009
• Est. Priority Date: 05/24/2005
• Status: Expired due to Fees

• Current Assignee: Robert Kuo-Chang Yang
• Original Assignee: Robert Kuo-Chang Yang
• Inventors: Yang, Robert Kuo-Chang
• Primary Examiner(s): Lee; Eugene
• Application Number:
  US11/234,519
• Publication Number:
  US 20060267044A1
• Time in Patent Office: 1,334 Days
• Field of Search: 257/492, 257/493, 257/335, 257/520, 257/E29.256
• US Class Current: 257/335
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/1087 characterised by the contact structure of the substrate region, e.g. for controlling or preventing bipolar effect
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/7816 Lateral DMOS transistors, i.e. LDMOS transistors
• CPC Class Codes: H01L 29/7823 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402

Abstract

Floating trenches are arranged in the layout of a single DMOS transistor or an array of DMOS transistors, the array forming a single power transistor. The trenches run perpendicular to the gate width direction either outside the transistor(s) or between rows of the transistors. The floating trenches are at a potential between the drain voltage and the substrate voltage (usually ground). The potentials of the opposing trenches cause merging depletion regions in the drift region. This merging shapes the field lines so as to increase the breakdown voltage of the transistor and provide other advantages. The technique is applicable to both lateral and vertical DMOS transistors.

Claims

1. A transistor structure comprising:

a lateral DMOS transistor comprising a source, a drain, a body region, a gate, and a drift region between the drain and the body region, the drift region having a conductivity type, the DMOS transistor being built on a substrate having a conductivity type opposite to that of the drift region; and

at least one pair of parallel opposing floating trenches, wherein a controllable current path exists in-between opposing floating trenches in the drift region, each floating trench comprising a conductive or semiconductor material that has no external electrical contact, the conductive or semiconductor material extending into the substrate and being insulated from any surrounding material by a dielectric,

the trenches having a length dimension running along the drift region between the source and drain, the gate having a width dimension running along the body region, the gate width dimension being substantially perpendicular to the length of the opposing floating trenches,

wherein an operating bias voltage applied to the drain capacitively couples a potential to the opposing floating trenches through the drift region and the substrate,

the opposing floating trenches being arranged so that the potential coupled to the opposing floating trenches causes a first lateral depletion region to extend from a first one of the opposing floating trenches toward an opposing second one of the opposing floating trenches, and causes a second lateral depletion region to extend from the second one of the opposing floating trenches toward the first one of the opposing floating trenches, such that the first lateral depletion region and the second lateral depletion region merge in the drift region at a certain drain bias.

2. The structure of claim 1 wherein the DMOS transistor comprises a two-dimensional array of lateral DMOS transistors arranged in rows, each lateral DMOS transistor comprising a source, a drain, a body region, a gate, and a drift region between the drain and the body region, the drift region having a conductivity type, the DMOS transistors being built on the substrate having a conductivity type opposite to that of the drift regions, the gate having a width dimension substantially perpendicular to a row of lateral DMOS transistors,

wherein at least one pair of parallel opposing floating trenches comprises a plurality of pairs of opposing floating trenches that run along and within a plurality of rows of lateral DMOS transistors, and a controllable current path exists in-between each pair of opposing floating trenches in the drift region, with the gate width dimension substantially perpendicular to the length of the opposing floating trenches.

3. The structure of claim 1 wherein the DMOS transistor comprises at least a row of lateral DMOS transistors, each lateral DMOS transistor comprising a source, a drain, a body region, a gate, and a drift region between the drain and the body region, the drift region having a conductivity type, the DMOS transistors being built on the substrate having a conductivity type opposite to that of the drift regions, the gate having a width dimension substantially perpendicular to a row of lateral DMOS transistors, wherein the parallel opposing floating trenches run on opposite sides of each row, there being at least a portion of a row of lateral DMOS transistors between a pair of opposing floating trenches, wherein a controllable current path exists in-between each pair of opposing floating trenches in the drift region, with the gate width dimension substantially perpendicular to the length of the opposing floating trenches.

4. The structure of claim 1 wherein the drain is a heavily doped region of a first conductivity type, the drain being formed in a lighter doped well region of the first conductivity type, the source, drain, well region, and body region being formed in

an epitaxial layer of the first conductivity type, the substrate being of a second conductivity type.

5. The structure of claim 4 wherein the drift region comprises a portion of the epitaxial layer under the gate.

6. The structure of claim 5 wherein at least one pair of parallel opposing floating trenches completely deplete the epitaxial region under the gate at a certain drain bias.

7. The structure of claim 4 further comprising a thick field oxide region between the gate and the well region.

8. The structure of claim 1 wherein each trench comprises an oxide liner and is at least partially filled with polysilicon that extends into the substrate.

9. The structure of claim 1 wherein the source is a region of a first conductivity type and the body region is of a second conductivity type, the structure further comprising a deep highly doped region of the second conductivity type extending completely through the body region for lowering a gain of a lateral parasitic bipolar transistor.

10. The structure of claim 1 wherein the spacing between opposing floating trenches is set to create a lateral depletion region that is able to merge in the drift region from each opposing floating trench at a drain bias voltage that is at or below a maximum rated voltage for the lateral DMOS transistor.

11. The structure of claim 1 wherein at least one pair of parallel opposing floating trenches completely depletes the drift region under the gate at a certain drain bias.

12. The structure of claim 1 further comprising a thick field oxide region between the gate and the drift region.

13. A lateral DMOS transistor structure comprising a source, a drain, a body region, a gate, and a drift region between the drain and the body region, wherein the source, drift region, and drain are of a first conductivity type, and the body region is of a second conductivity type, the structure further comprising an epitaxial layer of a first conductivity type in which is formed the source, drain, drift region, and body region, and further comprising a substrate of the second conductivity type and a highly doped buried layer of the first conductivity type between the substrate and the epitaxial layer;

and

at least one pair of parallel opposing floating trenches, wherein a controllable current path exists in-between opposing floating trenches in the drift region, each floating trench comprising a conductive or semiconductor material that has no external electrical contact, the conductive or semiconductor material being insulated from any surrounding material by a dielectric,

the trenches having a length dimension running along the drift region between the source and drain, the gate having a width dimension running along the body region, the gate width dimension being substantially perpendicular to the length of the opposing floating trenches,

wherein the opposing floating trenches are arranged such that an operating bias voltage applied to the drain capacitively couples a potential to the opposing floating trenches through the drift region and the substrate,

the opposing floating trenches being arranged so that the potential coupled to the opposing floating trenches causes a first lateral depletion region to extend from a first one of the opposing floating trenches toward an opposing second one of the opposing floating trenches, and causes a second lateral depletion region to extend from the second one of the opposing floating trenches toward the first one of the opposing floating trenches, such that the first lateral depletion region and the second lateral depletion region merge in the drift region at a certain drain bias.

14. The structure of claim 13 wherein each trench comprises an oxide liner and is at least partially filled with polysilicon, wherein the polysilicon extends into the substrate.

15. The structure of claim 13 wherein each trench comprises an oxide liner and is at least partially filled with polysilicon, wherein the polysilicon does not extend into the substrate, the structure fUrther comprising a substrate contact extending from the substrate to a surface of the structure running on outside edges of opposing floating trench pairs, wherein no transistor regions are present, for establishing capacitively coupling on the floating trenches.

16. The structure of claim 13 wherein each opposing floating trench causes at least 5000 of the lateral merging of depletion region in the epitaxial region between parallel opposing floating trenches at a certain drain bias.

17. The structure of claim 13 wherein the spacing between opposing floating trenches is set to create a lateral depletion region that is able to merge in the drift region from each opposing floating trench at a drain bias voltage that is at or below a maximum rated voltage for the lateral DMOS transistor.

18. The structure of claim 13 wherein at least one pair of parallel opposing floating trenches completely depletes the drift region under the gate at a certain drain bias.

19. The structure of claim 13 further comprising a thick field oxide region between the gate and the drift region.

20. The structure of claim 13 wherein the source is a region of a first conductivity type and the body region is of a second conductivity type, the structure further comprising a deep highly doped region of the second conductivity type extending completely through the body region for lowering a gain of a lateral parasitic bipolar transistor.