Monolithically integrated light emitting devices

• US 7,535,089 B2
• Filed: 11/01/2006
• Issued: 05/19/2009
• Est. Priority Date: 11/01/2005
• Status: Active Grant

• Current Assignee: Massachusetts Institute of Technology
• Original Assignee: Massachusetts Institute of Technology
• Inventors: Fitzgerald, Eugene A.
• Primary Examiner(s): LOUIE, WAI SING
• Application Number:
  US11/591,657
• Publication Number:
  US 20070105256A1
• Time in Patent Office: 930 Days
• Field of Search: 257/80, 257/82, 257/103, 257/444, 257/684
• US Class Current: 257/684
• CPC Class Codes: H01L 21/0245 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/0251 Graded layers
• CPC Class Codes: H01L 21/76254 with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
• CPC Class Codes: H01L 21/8258 the substrate being a semiconductor, using a combination of technologies covered by H01L21/8206, H01L21/8213 , H01L21/822, H01L21/8252, H01L21/8254 or H01L21/8256
• CPC Class Codes: H01L 27/0605 integrated circuits made of compound material, e.g. AIIIBV
• CPC Class Codes: H01L 27/144 Devices controlled by radiation
• CPC Class Codes: H01L 27/1446 in a repetitive configuration
• CPC Class Codes: H01L 27/14601 Structural or functional details thereof
• CPC Class Codes: H01L 27/14683 Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof not peculiar thereto H01L21/00
• CPC Class Codes: H01L 27/15 including semiconductor components having potential barriers, specially adapted for light emission
• CPC Class Codes: H01L 27/156 two-dimensional arrays
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 31/0328 including, apart from doping materials or other impurities, semiconductor materials provided for in two or more of groups H01L31/0272 - H01L31/032
• CPC Class Codes: H01L 31/143 the light source being a semiconductor device with at least one potential-jump barrier or surface barrier, e.g. light emitting diode
• CPC Class Codes: H01L 31/162 the light source being a semiconductor device with at least one potential-jump barrier or surface barrier, e.g. a light emitting diode
• CPC Class Codes: Y10S 438/933 Germanium or silicon or Ge-Si on III-V

Abstract

Methods and structures for monolithically integrating monocrystalline silicon and monocrystalline non-silicon materials and devices are provided. In one structure, a monolithically integrated semiconductor device structure comprises a silicon substrate and a first monocrystalline semiconductor layer disposed over the silicon substrate, wherein the first monocrystalline semiconductor layer has a lattice constant different from a lattice constant of relaxed silicon. The structure further includes an insulating layer disposed over the first monocrystalline semiconductor layer in a first region and a monocrystalline silicon layer disposed over the insulating layer in the first region. The structure includes at least one silicon-based electronic device including an element including at least a portion of the monocrystalline silicon layer. The structure also includes a second monocrystalline semiconductor layer disposed over at least a portion of the first monocrystalline semiconductor layer in a second region and absent from the first region, wherein the second monocrystalline semiconductor layer has a lattice constant different from the lattice constant of relaxed silicon. The structure includes at least one III-V light-emitting device including an active region including at least a portion of the second monocrystalline semiconductor layer.

Claims

1. A monolithically integrated semiconductor device structure comprising:

a silicon substrate;

a first monocrystalline semiconductor layer disposed over the silicon substrate, wherein the first monocrystalline semiconductor layer has a lattice constant different from a lattice constant of relaxed silicon;

an insulating layer disposed over the first monocrystalline semiconductor layer in a first region;

a monocrystalline silicon layer disposed over the insulating layer in the first region;

at least one silicon-based electronic device comprising an element including at least a portion of the monocrystalline silicon layer;

a second monocrystalline semiconductor layer disposed over at least a portion of the first monocrystalline semiconductor layer in a second region and absent from the first region, wherein the second monocrystalline semiconductor layer has a lattice constant different from the lattice constant of relaxed silicon; and

at least one III-V light-emitting device comprising an active region including at least a portion of the second monocrystalline semiconductor layer.

2. The structure of claim 1, wherein the second monocrystalline semiconductor layer has a composition different than that of the first monocrystalline layer.

3. The structure of claim 1, wherein the at least one silicon-based electronic device comprises a metal oxide semiconductor field-effect transistor.

4. The structure of claim 1, wherein the at least one III-V light-emitting device comprises a light emitting diode.

5. The structure of claim 1, wherein the at least one III-V light-emitting device comprises a plurality of light emitting diodes.

6. The structure of claim 5, wherein the plurality of light emitting diodes are arranged in a one-dimensional array.

7. The structure of claim 5, wherein the plurality of light emitting diodes are arranged in a two-dimensional array.

8. The structure of claim 7, wherein the two-dimensional array covers a rectangular area.

9. The structure of claim 1, further comprising:

an electrical interconnect coupling at least one silicon-based electronic device and the at least one III-V light-emitting device.

10. The structure of claim 9, wherein the at least one silicon-based electronic device is configured to drive the at least one III-V light-emitting device.

11. The structure of claim 1, further comprising:

at least one silicon-based photodetector comprising an active region including at least a portion of the monocrystalline silicon layer.

12. The structure of claim 1, further comprising:

an optical waveguide disposed between the at least one III-V light-emitting device and the at least one silicon-based photodetector, the optical waveguide configured to guide at least a portion of light emitted by the at least one III-V light-emitting device to the at least one silicon-based photodetector.

13. The structure of claim 1, wherein the second monocrystalline semiconductor layer is disposed in contact with the at least a portion of the first monocrystalline semiconductor layer.

14. The semiconductor structure of claim 1, wherein a top surface of the second monocrystalline semiconductor layer is substantially coplanar with a top surface of the monocrystalline silicon layer.

15. The semiconductor structure of claim 1, wherein the second monocrystalline semiconductor layer comprises a III-V semiconductor layer.

16. The semiconductor structure of claim 15, further comprising a silicon layer disposed over the III-V semiconductor layer, wherein the silicon layer is disposed in contact with the III-V semiconductor layer.

17. The semiconductor structure of claim 1, wherein the monocrystalline silicon layer comprises a relaxed silicon layer.

18. The semiconductor structure of claim 1, wherein the monocrystalline silicon layer comprises a strained silicon layer.

19. The semiconductor structure of claim 1, further comprising a second insulating layer disposed over the silicon substrate and under the first monocrystalline semiconductor layer.

20. The semiconductor structure of claim 1, wherein the first monocrystalline semiconductor layer comprises at least two monocrystalline semiconductor layers disposed over each other and having lattice constants different from each other and different from the lattice constant of relaxed silicon.

21. The semiconductor structure of claim 20, wherein the at least two monocrystalline semiconductor layers comprise a germanium layer and an InP layer.

22. The semiconductor structure of claim 20, wherein the at least two monocrystalline semiconductor layers comprise a germanium layer and a GaN layer.

23. The semiconductor structure of claim 20, wherein the at least two monocrystalline semiconductor layers comprise a GaAs layer and an InP layer.

24. The semiconductor structure of claim 20, wherein the at least two mono-crystalline semiconductor layers comprise a GaAs layer and a GaN layer.

25. The semiconductor structure of claim 1, wherein the first monocrystalline semiconductor layer comprises a germanium layer.

26. The semiconductor structure of claim 25, wherein the first monocrystalline semiconductor layer further comprises a silicon-germanium graded layer disposed under the germanium layer.

27. The semiconductor structure of claim 25, further comprising a second insulating layer disposed over the silicon substrate and under the germanium layer.

28. The semiconductor structure of claim 27, wherein the germanium layer is disposed in contact with the second insulating layer.

29. The semiconductor structure of claim 1, wherein the first monocrystalline semiconductor layer comprises a silicon-germanium layer.

30. The semiconductor structure of claim 29, wherein the first monocrystalline semiconductor layer further comprises a silicon-germanium graded layer disposed under the silicon-germanium layer.

31. The semiconductor structure of claim 29, further comprising a second insulating layer disposed over the silicon substrate and under the silicon-germanium layer.

32. The semiconductor structure of claim 31, wherein the silicon-germanium layer is disposed in contact with the second insulating layer.

33. The semiconductor structure of claim 1, wherein the first monocrystalline semiconductor layer comprises a III-V semiconductor layer.

34. The semiconductor structure of claim 33, wherein the III-V semiconductor layer comprises a GaN layer.

35. The semiconductor structure of claim 33, wherein the III-V semiconductor layer comprises a GaAs layer.

36. The semiconductor structure of claim 33, wherein the first monocrystalline semiconductor layer further comprises a germanium layer disposed under the III-V semiconductor layer.

37. The semiconductor structure of claim 33, wherein the first monocrystalline semiconductor layer further comprises a silicon-germanium layer disposed under the III-V semiconductor layer.

38. The semiconductor structure of claim 33, wherein the first monocrystalline semiconductor layer further comprises a silicon-germanium graded layer disposed under the III-V semiconductor layer.

39. The semiconductor structure of claim 1, wherein the silicon substrate has a diameter of at least 150 millimeters.

40. The semiconductor structure of claim 1, wherein the silicon substrate has a diameter of at least 200 millimeters.

41. A monolithically integrated semiconductor device structure comprising:

a silicon substrate;

a first monocrystalline semiconductor layer disposed over the silicon substrate, wherein the first monocrystalline semiconductor layer has a lattice constant different from a lattice constant of relaxed silicon;

a monocrystalline silicon layer disposed over the first monocrystalline semiconductor layer in the first region;

at least one silicon-based electronic device comprising an element including at least a portion of the monocrystalline silicon layer;

a second monocrystalline semiconductor layer disposed on at least a portion of the first monocrystalline semiconductor layer in a second region and absent from the first region, wherein the second monocrystalline semiconductor layer has a lattice constant different from the lattice constant of relaxed silicon; and

at least one III-V light-emitting device comprising an active region including at least a portion of the second monocrystalline semiconductor layer.

42. The semiconductor structure of claim 41, further comprising a layer in the first region disposed between the monocrystalline silicon layer and the first monocrystalline semiconductor layer.

43. The semiconductor structure of claim 42, wherein the layer in the first region disposed between the monocrystalline silicon layer and the first monocrystalline semiconductor layer is a non-insulating layer.

44. The semiconductor structure of claim 42, wherein the layer in the first region disposed between the monocrystalline silicon layer and the first monocrystalline semiconductor layer is an insulating layer.

45. The semiconductor structure of claim 41, wherein at least a portion of the second monocrystalline semiconductor layer has a composition different than a composition of the first monocrystalline layer.