Programmable current output and common-mode voltage buffer

• US 7,535,258 B1
• Filed: 11/06/2006
• Issued: 05/19/2009
• Est. Priority Date: 12/15/2004
• Status: Active Grant

• Current Assignee: Lattice Semiconductor Corporation
• Original Assignee: Lattice Semiconductor Corporation
• Inventors: Johnson, Phillip L., Cartney, Gregory S., Andrews, William B.
• Primary Examiner(s): Tan; Vibol
• Assistant Examiner(s): Crawford; Jason
• Application Number:
  US11/593,274
• Time in Patent Office: 925 Days
• Field of Search: 326/63, 326/68, 326 82- 83, 326 86- 87, 327108-109
• US Class Current: 326/82
• CPC Class Codes: H03F 2203/45008 the addition of two signals being made by a resistor addition circuit for producing the common mode signal
• CPC Class Codes: H03F 2203/45048 Calibrating and standardising a dif amp
• CPC Class Codes: H03F 2203/45082 the common mode signal being taken or deducted from the one or more outputs of the differential amplifier
• CPC Class Codes: H03F 2203/45418 the CMCL comprising a resistor addition circuit
• CPC Class Codes: H03F 2203/45424 the CMCL comprising a comparator circuit
• CPC Class Codes: H03F 2203/45504 the CSC comprising more than one switch
• CPC Class Codes: H03F 2203/45681 the LC comprising offset compensating means
• CPC Class Codes: H03F 3/45237 Complementary long tailed pairs having parallel inputs and being supplied in series
• CPC Class Codes: H03F 3/4565 Controlling the common source circuit of the differential amplifier
• CPC Class Codes: H03K 19/018585 programmable

Abstract

A buffer for a programmable logic device has programmable current sink and source circuitry and an independently programmable common-mode voltage reference source. An amplifier, responsive to a common-mode voltage detector and the voltage reference source, forces a common-mode voltage of an output signal from the buffer to approximate the voltage from the common-mode voltage reference source.

Claims

1. A programmable logic device having a buffer, the buffer comprising:

at least one controlled current source;

at least one input node adapted to receive at least one input signal;

first and second output nodes adapted to present first and second output signals;

a detector adapted to generate a sampled voltage corresponding to a common-mode voltage of the output nodes;

a controlled voltage source adapted to generate a common-mode reference voltage; and

,

an amplifier adapted to adjust the at least one controlled current source in response to the sampled voltage and the common-mode reference voltage,

wherein;

the controlled voltage source is controlled independently of the at least one controlled current source; and

the at least one controlled current source and the controlled voltage source are adapted to be programmably controlled and are each independently programmable; and

wherein the programmably controlled voltage source comprises;

a reference voltage source adapted to produce a reference voltage;

a voltage divider, coupled to the reference voltage source, adapted to produce a plurality of output voltages; and

a plurality of switches adapted to selectively couple one of the plurality of voltages from the voltage divider to an output node,

wherein a signal on the output node is the common-mode reference voltage.

2. The programmable logic device of claim 1, wherein:

the amplifier adjusts the at least one controlled current source so that the common-mode voltage is approximately equal to the common-mode reference voltage; and

the programmable logic device is implemented as a single integrated circuit.

3. The programmable logic device of claim 1, wherein the at least one programmably controlled current source comprises:

source current circuitry adapted to be programmably controlled to selectively generate any one of a plurality of different total source currents;

sink current circuitry adapted to be programmably controlled to selectively generate any one of a plurality of different total sink currents; and

,

first switch circuitry adapted to selectively apply at least one of a total source current and a total sink current to the first or second output nodes based on the at least one input signal.

4. The programmable logic device of claim 3, wherein the programmably controlled voltage source comprises second switch circuitry adapted to selectively supply one of a plurality of voltages as the common-mode reference voltage.

5. The programmable logic device of claim 3, wherein:

the source current circuitry comprises N switched current sources connected in parallel; and

,

the sink current circuitry comprises M switched current sinks connected in parallel.

6. The programmable logic device of claim 5, wherein:

the programmably controlled voltage source comprises a plurality of switches;

the N switched current sources are independently programmable;

the M switched current sources are independently programmable; and

,

the plurality of switches of the programmably controlled voltage source are independently programmable.

7. The programmable logic device of claim 1, wherein the programmably controlled voltage source further comprises a voltage-follower adapted to couple the reference voltage to the voltage divider.

8. The programmable logic device of claim 1, wherein the reference voltage source is adapted to derive the reference voltage from a power source of the programmable logic device.

9. The programmable logic device of claim 1 wherein the reference voltage source is adapted to derive the reference voltage from a source external to the programmable logic device.

10. The programmable logic device of claim 1, wherein the reference voltage source comprises switches adapted to selectively couple to a node as the reference voltage either 1) a voltage derived from a power source of the programmable logic device or 2) a source external to the programmable logic device.

11. The programmable logic device of claim 1, wherein one of the plurality of output voltages of the voltage divider is approximately equal to the reference voltage.

12. A programmable logic device having a buffer, the buffer comprising:

at least one controlled current source;

at least one input node adapted to receive at least one input signal;

first and second output nodes adapted to present first and second output signals;

a detector adapted to generate a sampled voltage corresponding to a common-mode voltage of the output nodes;

a controlled voltage source adapted to generate a common-mode reference voltage; and

an amplifier adapted to adjust the at least one controlled current source in response to the sampled voltage and the common-mode reference voltage,

wherein;

the controlled voltage source is controlled independently of the at least one controlled current source; and

the at least one controlled current source and the controlled voltage source are adapted to be programmably controlled and are each independently programmable,

wherein the at least one programmably controlled current source comprises a first plurality of programmably controlled current sources connected in parallel and programmably controllable such that at least two of the parallel current sources are selected at the same time.

13. A programmable logic device having a buffer, the buffer comprising:

at least one controlled current source;

at least one input node adapted to receive at least one input signal;

first and second output nodes adapted to present first and second output signals;

a detector adapted to generate a sampled voltage corresponding to a common-mode voltage of the output nodes;

a controlled voltage source adapted to generate a common-mode reference voltage; and

,

an amplifier adapted to adjust the at least one controlled current source in response to the sampled voltage and the common-mode reference voltage,

wherein;

the controlled voltage source is controlled independently of the at least one controlled current source; and

the at least one controlled current source and the controlled voltage source are adapted to be programmably controlled and are each independently programmable,

wherein;

the at least one programmably controlled current source comprises at least first, second, and third programmably controlled current sources, each having a gate, connected in parallel;

a first switch connected between the gates of the first and second parallel current sources; and

a second switch connected between the gates of the second and third parallel current sources.

14. A programmable logic device having a buffer, the buffer comprising:

at least one controlled current source;

at least one input node adapted to receive at least one input signal;

first and second output nodes adapted to present first and second output signals;

a detector adapted to generate a sampled voltage corresponding to a common-mode voltage of the output nodes;

a controlled voltage source adapted to generate a common-mode reference voltage; and

,

an amplifier adapted to adjust the at least one controlled current source in response to the sampled voltage and the common-mode reference voltage,

wherein;

the controlled voltage source is controlled independently of the at least one controlled current source; and

the at least one controlled current source and the controlled voltage source are adapted to be programmably controlled and are each independently programmable,

wherein the output of the amplifier is connected to the gate of an additional current source connected in parallel to the at least one programmably controlled current source.

15. A programmable logic device having a buffer, the buffer comprising:

at least one controlled current source;

at least one input node adapted to receive at least one input signal;

first and second output nodes adapted to present first and second output signals;

a detector adapted to generate a sampled voltage corresponding to a common-mode voltage of the output nodes;

a controlled voltage source adapted to generate a common-mode reference voltage; and

,

an amplifier adapted to adjust the at least one controlled current source in response to the sampled voltage and the common-mode reference voltage,

wherein;

the controlled voltage source is controlled independently of the at least one controlled current source; and

the at least one controlled current source and the controlled voltage source are adapted to be programmably controlled and are each independently programmable,

wherein the buffer further comprises;

first and second input nodes adapted to receive first and second input signals;

a first pair of transistors connected in series at the first output node; and

a second pair of transistors connected in series at the second output node, wherein;

the first input node is connected to apply the first input signal to the gates of the first pair of series-connected transistors; and

the second input node is connected to apply the second input signal to the gates of the second pair of series-connected transistors.

16. The programmable logic device of claim 15, wherein:

the first pair of series-connected transistors comprises a n-type transistor and a p-type transistor; and

the second pair of series-connected transistors comprises a n-type transistor and a p-type transistor.

17. A programmable logic device having a buffer, the buffer comprising:

at least one controlled current source;

at least one input node adapted to receive at least one input signal;

first and second output nodes adapted to present first and second output signals;

a detector adapted to generate a sampled voltage corresponding to a common-mode voltage of the output nodes;

a controlled voltage source adapted to generate a common-mode reference voltage; and

,

an amplifier adapted to adjust the at least one controlled current source in response to the sampled voltage and the common-mode reference voltage,

wherein;

the controlled voltage source is controlled independently of the at least one controlled current source; and

the at least one controlled current source and the controlled voltage source are adapted to be programmably controlled and are each independently programmable,

wherein the programmable controlled voltage source comprises a voltage divider coupled to a reference voltage source and adapted to produce a plurality of output voltages, wherein the voltage divider supplies the plurality of different voltages to the output node.