Dynamic memory word line driver scheme

• US 7,535,749 B2
• Filed: 03/30/2006
• Issued: 05/19/2009
• Est. Priority Date: 04/06/1990
• Status: Expired due to Fees

• Current Assignee: Mosaid Technologies Incorporated (MOSAID Technologies Inc. (f/k/a Conversant Intellectual Property Management))
• Original Assignee: Mosaid Technologies Incorporated (MOSAID Technologies Inc. (f/k/a Conversant Intellectual Property Management))
• Inventors: Lines, Valerie L.
• Primary Examiner(s): Luu; Pho M.
• Application Number:
  US11/396,306
• Publication Number:
  US 20070025137A1
• Time in Patent Office: 1,146 Days
• Field of Search: 365/149, 365/150, 365/230.06, 365/154, 365/189.12, 365/230.01
• US Class Current: 365/149
• CPC Class Codes: G11C 11/4085 Word line control circuits, e.g. word line drivers, - boosters, - pull-up, - pull-down, - precharge
• CPC Class Codes: G11C 8/08 Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines

Abstract

A circuit which accurately controls the word line (pass transistor gate) driving voltage to a voltage which is both controlled and is not significantly greater than is needed to drive the word line. The circuit eliminates the need for a double-boot-strapping circuit, and ensures that no voltages exceed that necessary to fully turn on a memory cell access transistor. Voltages in excess of that which would reduce reliability are avoided, and accurate driving voltages are obtained. A DRAM includes word lines, memory cells having enable inputs connected to the word lines, a gate receiving word line selecting signals at first logic levels V_ss and V_dd, and for providing a select signal at levels V_ss and V_dd, a high voltage supply source V_pp which is higher in voltage than V_dd, a circuit for translating the select signals at levels V_ss and V_dd to levels V_ss and V_pp and for applying it directly to the word lines whereby an above V_dd voltage level word line is achieved without the use of double boot-strap circuits.

Claims

1. A dynamic random access memory comprising:

a voltage supply having a controlled high supply voltage level;

word lines;

memory cells, each comprising a charge storage capacitor and an access transistor for storing a logic level on the storage capacitor, the access transistor having an enable input connected to a word line; and

a word line selection circuit comprising a pair of cross-coupled transistors coupled drain-to-gate and having respective sources receiving current from the controlled high supply voltage level, the selection circuit receiving logic signals having only levels that are less than the controlled high supply voltage level to drive a selected word line to the controlled high supply voltage level.

2. A dynamic random access memory as claimed in claim 1 wherein the selected word line is driven to the controlled high supply voltage level through an additional transistor enabled from the drain of one of the cross-coupled transistors.

3. A dynamic random access memory as claimed in claim 1 wherein the selected word line is driven to the controlled high supply voltage level from a secondary decoder output through an additional transistor enabled from the drain of one of the cross-coupled transistors.

4. A dynamic random access memory as claimed in claim 1 wherein the cross-coupled transistors are P-channel FETs and the drains of the cross-coupled transistors are pulled down by respective N-channel FETs.

5. A dynamic random access memory comprising:

a voltage supply having a controlled high supply voltage level Vpp;

word lines that enable memory cell access transistors; and

memory cells, each comprising a charge storage capacitor and an access transistor for storing a logic level on the storage capacitor, the access transistor having an enable input coupled to a word line; and

a word line selection circuit comprising a pair of cross-coupled transistors having their respective sources directly connected to the controlled high supply voltage level Vpp, the selection circuit receiving logic signals having only logic voltage levels that are less than the controlled voltage level Vpp to produce a control signal selectively having the controlled high supply voltage level Vpp or a Vss voltage level, the control signal selectively driving the word line to the controlled high supply voltage level Vpp.

6. A dynamic random access memory as claimed in claim 5 wherein the selected word line is driven to the controlled high supply voltage level Vpp through an additonal transistor enabled from the drain of one of the cross-coupled transistors.

7. A dynamic random access memory as claimed in claim 5 wherein the selected word line is driven to the controlled high supply voltage level Vpp from a secondary decoder output through an additional transistor enabled from the drain of one of the cross-coupled transistors.

8. A dynamic random access memory as claimed in claim 5 wherein the cross-coupled transistors are P-channel FETs and the drains of the cross-coupled transistors are pulled down by respective N-channel FETs.

9. A method of selecting word lines and writing to memory cells in a dynamic random access memory to store a voltage level in a memory cell comprising:

supplying a controlled high supply voltage level that is greater than the voltage level stored in the memory cell to a level shifter circuit, the level shifter circuit comprising a pair of cross-coupled transistors connected drain-to-gate and having respective sources receiving current from the controlled high supply voltage;

providing logic signals having only logic levels that are less than the controlled high supply voltage level to the level shifter circuit to selectively produce a control signal having a logic state at the controlled high supply voltage level and another logic state at a low voltage level;

driving a selected dynamic random access memory word line to the controlled high supply voltage level in response to the control signal; and

writing a voltage from a bit line into a memory cell capacitor associated with the selected word line to store a voltage representative of a logic level in the selected memory cell.

10. A method as claimed in claim 9 wherein the selected word line is driven by enabling an additional transistor from the drain of one of the cross-coupled transistors, the additional transistor being coupled between the controlled high supply voltage level and the word line.

11. A method as claimed in claim 10 wherein the drain of the additional transistor is coupled to the word line.

12. A method as claimed in claim 10 wherein the additional transistor is a P-channel FET.

13. A method as claimed in claim 9 wherein the selected word line is driven by enabling an additional transistor from the drain of one of the cross-coupled transistors, the additional transistor being coupled between a secondary decoder output, having an output voltage level at the controlled high supply voltage level, and the word line.

14. A method as claimed in claim 13 wherein the additional transistor is a P-channel FET.

15. A method as claimed in claim 13 wherein the drain of the additional transistor is coupled to the word line.

16. A method as claimed in claim 9 wherein the cross-coupled transistors are P-channel FETs and the drains of the cross-coupled transistors are pulled down by respective N-channel FETs.

17. A method as claimed in claim 9 wherein the selected word line is driven without using a double bootstrapping circuit.

18. A method of selecting word lines and writing to memory cells in a dynamic random access memory to store a voltage level in a memory cell comprising:

supplying a controlled high supply voltage level that is greater than the voltage level stored in the memory cell to a level shifter circuit, the level shifter circuit comprising a pair of cross-coupled transistors connected drain-to-gate and having respective sources coupled to the controlled high supply voltage level;

providing logic signals having only logic levels that are less than the controlled high supply voltage level to the level shifter circuit to selectively produce a control signal having a logic state at the controlled high supply voltage level and another logic state at a low voltage level;

driving a selected dynamic random access memory word line from a decoded secondary output at the controlled high supply voltage level in response to the control signal; and

writing a voltage from a bit line into a memory cell capacitor associated with the selected word line to store a voltage representative of a logic level in the selected memory cell.

19. A method of selecting word lines and writing to memory cells in a dynamic random access memory, the method comprising:

supplying a controlled high supply voltage level Vpp from a high voltage supply to a level shifter circuit, the level shifter circuit comprising at least first and second transistors having their respective sources directly connected to the controlled high supply voltage level Vpp, the drain of the first transistor applying current to a first node, the drain of the second transistor applying current to a second node, the first and second transistors being gated from the second and first nodes, respectively;

providing a decoded address input signal, selectively having only logic voltage levels that are less than the controlled voltage level Vpp, to the level shifter circuit to produce a control signal selectively having the controlled high supply voltage level Vpp or a Vss voltage level;

selectively driving the word line to the controlled high supply voltage level Vpp in response to the control signal; and

writing a voltage from a bit line into a memory cell capacitor associated with the selected word line to store a voltage representative of a logic level in the selected memory cell.

20. A method as claimed in claim 19 wherein the selected word line is driven by enabling an additional transistor from the drain of one of the first and second transistors, the additional transistor being coupled between the controlled high supply voltage level Vpp and the word line.

21. A method as claimed in claim 19 wherein the selected word line is driven by enabling an additional transistor from the drain of one of the first and second transistors, the additional transistor being coupled between a secondary decoder output, having an output voltage level at the controlled high supply voltage level Vpp, and the word line.

22. A method as claimed in claim 19 wherein the first and second transistors are P-channel FETs and the drains of the first and second transistors are pulled down by respective N-channel FETs.

23. A method for storing a voltage level in a memory cell coupled to a word line and a bit line of a dynamic random access memory, the method comprising:

providing a controlled high supply voltage level that is greater than the voltage level stored in a memory cell to a level shifter, the level shifter comprising a pair of transistors, the drains and gates being cross-coupled to each other, the source of each of the transistors being provided with the controlled high supply voltage;

providing logic signals to the level shifter for producing a control signal, each of the logic signal having two levels, the higher level of which is less than the controlled high supply voltage level, the control signal having a logic state at the controlled high supply voltage level;

selectively driving a word line to the controlled high supply voltage level in response to the control signal; and

writing a voltage from a bit line into a memory cell capacitor associated with the driven word line to store a voltage representative of a logic level in the memory cell.

24. A method as claimed in claim 23 wherein the step of selectively driving comprises enabling an additional transistor to pass the controlled high supply voltage level to the word line in response to the control signal.

25. A method as claimed in claim 24 wherein the step of enabling comprises enabling the additional transistor comprising a P-channel FET.

26. A method as claimed in claim 23 wherein the step of selectively driving comprises enabling an additional transistor to pass the controlled high supply voltage from a secondary decoder output to the word line in response to the control signal, the secondary decoder output having an output voltage level at the controlled high supply voltage level.

27. A method as claimed in claim 26 wherein the step of enabling comprises enabling the additional transistor comprising a P-channel FET.

28. A method as claimed in claim 23 wherein the pair of transistors comprises a pair of P-channel FETs, the drains of which are pulled down by respective N-channel FETs.

29. A method as claimed in claim 23 wherein the step of selectively driving is performed without using a double bootstrapping circuit.

30. A dynamic random access memory comprising:

a voltage supply having a controlled high supply voltage level;

word lines;

memory cells, each comprising a charge storage capacitor and an access transistor for storing a logic level on the storage capacitor, the access transistor having an enable input coupled to a word line; and

a word line selection circuit comprising a pair of cross-coupled transistors and pull down transistors coupled to the drains of the cross-coupled transistors, the selection circuit receiving logic signals having only logic levels that are less than the controlled high supply voltage level to drive a selected word line to the controlled high supply voltage level, the logic signals being applied only to the pull down transistors.

31. A dynamic random access memory as claimed in claim 30 wherein the selected word line is driven to the controlled high supply voltage level through an additional transistor enabled from the drain of one of the cross-coupled transistors.

32. A dynamic random access memory as claimed in claim 30 wherein the selected word line is driven to the controlled high supply voltage level from a secondary decoder output through an additional transistor enabled from the drain of one of the cross-coupled transistors.

33. A dynamic random access memory as claimed in claim 30 wherein the cross-coupled transistors are P-channel FETs and the drains of the cross-coupled transistors are pulled down by respective N-channel FETs.

34. A method of selecting word lines and writing to memory cells in a dynamic random access memory to store a voltage level in a memory cell comprising:

supplying a controlled high supply voltage level that is greater than the voltage level stored in the memory cell to a level shifter circuit, the level shifter circuit comprising a pair of cross-coupled transistors and pull down transistors coupled to the drains of the cross-coupled transistors;

providing selection logic signals having only logic levels that are less than the controlled high supply voltage level to the level shifter circuit to selectively produce a control signal having a logic state at the controlled high supply voltage level and another logic state at a low voltage level, the selection logic signals being coupled only to the pull down transistors;

driving a selected dynamic random access memory word line to the controlled high supply voltage level in response to the control signal; and

writing a voltage from a bit line into a memory cell capacitor associated with the selected word line to store a voltage representative of a logic level in the selected memory cell.

35. A method as claimed in claim 34 wherein the selected word line is driven by enabling an additional transistor from the drain of one of the cross-coupled transistors, the pass transistor being coupled between the controlled high supply voltage level and the word line.

36. A method as claimed in claim 35 wherein the drain of the additional transistor is coupled to the word line.

37. A method as claimed in claim 35 wherein the additional transistor is a P-channel FET.

38. A method as claimed in claim 34 wherein the selected word line is driven by enabling an additional transistor from the drain of one of the cross-coupled transistors, the additional transistor being coupled between a secondary decoder output, having an output voltage level at the controlled high supply voltage level, and the word line.

39. A method as claimed in claim 38 wherein the drain of the additional transistor is coupled to the word line.

40. A method as claimed in claim 38 wherein the additional transistor is a P-channel FET.

41. A method as claimed in claim 34 wherein the cross-coupled transistors are P-channel FETs and the drains of the cross-coupled transistors are pulled down by respective N-channel FETs.

42. A method as claimed in claim 34 wherein the selected word line is driven without using a double bootstrapping circuit.

43. A method of selecting word lines and writing to memory cells in a dynamic random access memory to store a voltage level in a memory cell comprising:

supplying a controlled high supply voltage level that is greater than the voltage level stored in the memory cell to a level shifter circuit, the level shifter circuit comprising a pair of cross-coupled transistors and pull down transistors coupled to the drains of the cross-coupled transistors;

providing lower voltage level logic signals having only logic levels that are less than the controlled high supply voltage level to the level shifter circuit to selectively produce a control signal having a logic state at the controlled high supply voltage level and another logic state at a low voltage level, the lower voltage level logic signals being applied only to the pull down transistors;

driving a selected dynamic random access memory word line from a decoded secondary output at the controlled high supply voltage level in response to the control signal; and

writing a voltage from a bit line into a memory cell capacitor associated with the selected word line to store a voltage representative of a logic level in the selected memory cell.