Time-dependent compensation currents in non-volatile memory read operations

• US 7,535,769 B2
• Filed: 04/24/2008
• Issued: 05/19/2009
• Est. Priority Date: 06/20/2005
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk Corporation (Western Digital Corporation)
• Inventors: Cernea, Raul-Adrian
• Primary Examiner(s): Nguyen; Dang T
• Application Number:
  US12/108,710
• Publication Number:
  US 20080198656A1
• Time in Patent Office: 390 Days
• Field of Search: 365/185.22, 365/185.17, 365/189.01, 365/189.04, 365/189.07
• US Class Current: 365/185.22
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 7/02 with means for avoiding parasitic signals
• CPC Class Codes: G11C 7/12 Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines

Abstract

Shifts in the apparent charge stored on a floating gate of a non-volatile memory cell can occur because of coupling of an electric field based on the charge stored in adjacent floating gates. The shift in apparent charge can lead to erroneous readings by raising the apparent threshold voltage, and consequently, lowering the sensed conduction current of a memory cell. The read process for a selected memory cell takes into account the state of one or more adjacent memory cells. If an adjacent memory cell is in one or more of a predetermined set of programmed states, a compensation current can be provided to increase the apparent conduction current of the selected memory cell. An initialization voltage is provided to the bit line of the programmed adjacent memory cell to induce a compensation current between the bit line of the programmed adjacent memory cell and the bit line of the selected memory cell.

Claims

1. A method of reading data from non-volatile storage, comprising:

reading a first non-volatile storage element of a first string of non-volatile storage elements to determine whether said first non-volatile storage element is programmed to at least one predetermined state;

reading a second non-volatile storage element of a second string of non-volatile storage elements to determine whether said second non-volatile storage element is programmed to said at least one predetermined state;

reading a third non-volatile storage element of a third string of non-volatile storage elements using at least one compensation current and a first sampling period if at least one of said first non-volatile storage element and said second non-volatile storage element is programmed to said at least one predetermined state; and

reading said third non-volatile storage element using a second sampling period if said first non-volatile storage element and said second non-volatile storage element are not programmed to said at least one predetermined state.

2. The method of claim 1, further comprising:

providing a first initialization voltage to a bit line of said first string if said first non-volatile storage element is determined to be in said at least one predetermined state so as to induce a first compensation current; and

providing a second initialization voltage to a bit line of said second string if said second non-volatile storage element is determined to be in said at least one predetermined state so as to induce a second compensation current;

wherein reading said third non-volatile storage element includes using said first compensation current, said second compensation current and said first sampling period if said first non-volatile storage element and said second non-volatile storage element are programmed to said at least one predetermined state.

3. The method of claim 1, wherein said first sampling period and said second sampling period include an equal duration, said first sampling period occurring earlier in time than said second sampling period.

4. The method of claim 1, wherein:

said first non-volatile storage element, said second non-volatile storage element and said third non-volatile storage element are connected to a first word line; and

reading said first non-volatile storage element and said second non-volatile storage element occurs simultaneously and includes an additional reading of said third non-volatile storage element to determine whether said third non-volatile storage element is programmed to said at least one predetermined state.

5. The method of claim 1, wherein:

reading said third non-volatile storage element using a second sampling period does not include using compensation.

6. The method of claim 1, wherein:

non-volatile storage elements of said first string, said second string and said third string are programmable to at least three programmed states including a highest programmable state; and

said at least one predetermined state includes said highest programmable state.

7. The method of claim 1, wherein:

said first string of non-volatile storage elements is a first NAND string of serially connected flash memory cells;

said second string of non-volatile storage elements is a second NAND string of serially connected flash memory cells; and

said third string of non-volatile storage elements is a third NAND string of serially connected flash memory cells.

8. A method of reading data from non-volatile storage, comprising:

reading a first non-volatile storage element of a first string of non-volatile storage elements;

reading a second non-volatile storage element of a second string of non-volatile storage elements using compensation and a first sampling period if said first non-volatile storage element is programmed to a first predetermined state;

reading said second non-volatile storage element using compensation and a second sampling period if said first non-volatile storage element is programmed to a second predetermined state; and

reading said second non-volatile storage element using a third sampling period if said first non-volatile storage element is not programmed to said first predetermined state or said second predetermined state.

9. The method of claim 8, further comprising:

providing an initialization voltage to a bit line of said first string of non-volatile storage elements if said first non-volatile storage element is determined to be in said first predetermined state or said second predetermined state, said providing inducing a compensation current in said second string of non-volatile storage elements that dissipates over time;

wherein reading said second non-volatile storage element during said first sampling period uses a first compensation corresponding to a level of said compensation current during said first sampling period;

wherein reading said second non-volatile storage element during said third sampling period uses a second compensation corresponding to a level of said compensation current during said second sampling period;

wherein said first predetermined state includes larger threshold voltages than said second predetermined state;

wherein said first compensation is larger than said second compensation; and

wherein said first sampling period is earlier in time than said second sampling period and said third sampling period.

10. The method of claim 8, further comprising:

providing a first initialization voltage to a bit line of said first string of non-volatile storage elements if said first non-volatile storage element is determined to be in said first predetermined state; and

providing a second initialization voltage to said bit line of said first string of non-volatile storage elements if said first non-volatile storage element is determined to be in said second predetermined state;

wherein said first predetermined state includes larger threshold voltages than said second predetermined state;

wherein said first initialization voltage is lower than said second initialization voltage.

11. The method of claim 8, wherein:

said first string of non-volatile storage elements is a first NAND string of serially connected flash memory cells;

said second string of non-volatile storage elements is a second NAND string of serially connected flash memory cells;

said first non-volatile storage element is connected to a first word line; and

said second non-volatile storage element is connected to said first word line.

12. A method of reading non-volatile storage, comprising:

determining which non-volatile storage elements of a set of non-volatile storage elements are programmed to at least one predetermined state, said non-volatile storage elements of said set being coupled to a first word line and consecutive bit lines;

for each non-volatile storage element determined not to be in said at least one predetermined state and having at least one adjacent non-volatile storage element of the set that is determined to be in said at least one predetermined state, reading said each non-volatile storage element using compensation and a first sampling period; and

for each non-volatile storage element determined not to be in said at least one predetermined state and not having at least one adjacent non-volatile storage element in said at least one predetermined state, reading said each non-volatile storage element using a second sampling period.

13. The method of claim 12, further comprising:

for each non-volatile storage element determined not to be in said at least one predetermined state, pre-charging a bit line associated with said each non-volatile storage element;

wherein said first sampling period begins at a first time after said pre-charging and said second sampling period begins a second time after said pre-charging, said first time being before said second time.

14. The method of claim 12, further comprising:

providing an initialization voltage to a bit line associated with each non-volatile storage element determined to be in said at least one predetermined state after said pre-charging, said initialization voltage inducing a compensation current in a bit line associated with each adjacent non-volatile storage element not in said at least one predetermined state.

15. The method of claim 14, wherein said second time corresponds to an expected time after which said compensation current has dissipated.

16. The method of claim 12, wherein said set of non-volatile storage elements is a set of multi-state NAND flash memory cells.