Hybrid wired and wireless chip-to-chip communications
First Claim
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1. A method for wireless communications between a first node and a second node, comprising:
- delivering a timing reference signal via a wired interconnect structure to the first node and the second node;
transmitting a radio signal in response to the timing reference signal at the first node, the radio signal carrying data;
receiving the radio signal in response to the timing reference signal at the second node;
executing a synchronization process to set at least one of a transmit drive point on the first node and a receive sample point on the second node, and including transmitting a control signal related to the synchronization process via a wired interconnect structure between the first and second node; and
producing a transmit drive signal in response to the timing reference signal at the first node and producing a receive sample signal in response to the timing reference signal at the second node, and adjusting the timing based on the synchronization process of at least one of the transmit drive signal at the first node and the receive sample signal at the second node to coordinate communication between the first and second nodes.
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Abstract
A hybrid wireless and wired system distributes precise timing and synchronization information among the nodes over a wired interconnect structure while data is transmitted wirelessly using ultra-wideband radio over short distances. The timing information communicated over the wired interconnect structure is used to establish a baseline timing reference for the wireless transmitters, receivers and transceivers on the nodes of the communication network. Using a common timing reference, a mesochronous communication system is established for chip-to-chip wireless data transmission.
157 Citations
32 Claims
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1. A method for wireless communications between a first node and a second node, comprising:
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delivering a timing reference signal via a wired interconnect structure to the first node and the second node; transmitting a radio signal in response to the timing reference signal at the first node, the radio signal carrying data; receiving the radio signal in response to the timing reference signal at the second node; executing a synchronization process to set at least one of a transmit drive point on the first node and a receive sample point on the second node, and including transmitting a control signal related to the synchronization process via a wired interconnect structure between the first and second node; and producing a transmit drive signal in response to the timing reference signal at the first node and producing a receive sample signal in response to the timing reference signal at the second node, and adjusting the timing based on the synchronization process of at least one of the transmit drive signal at the first node and the receive sample signal at the second node to coordinate communication between the first and second nodes. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13)
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14. A method for wireless communications between a first node and a second node, comprising:
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delivering a timing reference signal via a wired interconnect structure to the first node and the second node; transmitting a radio signal in response to the timing reference signal at the first node, the radio signal carrying data; and receiving the radio signal in response to the timing reference signal at the second node;
including;producing a transmit drive signal in response to the timing reference signal at the first node and producing a receive sample signal in response to the timing reference signal at the second node, and adjusting the timing of at least one of the transmit drive signal at the first node and the receive sample signal at the second node, wherein the adjusting includes; producing a phase locked clock signal having a frequency greater than 1 GHz in response to the timing reference signal, providing a source for a plurality of phase shifted copies of the phase locked clock signal and selecting one of the plurality of phase shifted copies in response to a control parameter, where the plurality of phase shifted copies includes at least 50 phase shifted copies.
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15. A system comprising:
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a first integrated circuit and a second integrated circuit; a wired interconnect structure coupled to the first and second integrated circuits; and a clock circuit coupled to the wired interconnect structure, the clock circuit transmitting a timing reference signal on the wired interconnect structure;
whereinthe first integrated circuit includes; a data source; a timing reference signal input adapted to receive the timing reference signal via the wired interconnect structure; a transmit timing circuit which produces a transmit timing signal in response to the timing reference signal; and a radio transmitter coupled to the transmit timing circuit and the data source which transmits a radio signal carrying data from the data source in response to the transmit timing signal; logic which executes a synchronization process to set timing for the transmit timing signal for the radio transmitter, the synchronization process including communication of a control signal related to the synchronization process via a wired interconnect structure with the second integrated circuit; circuitry on the first integrated circuit responsive to the synchronization process to adjust timing of the transmit timing signal to coordinate communication between the first and second integrated circuits; and the second integrated circuit includes; a timing reference signal input adapted to receive the timing reference signal via the wired interconnect structure; a receive timing circuit which produces a receive timing signal in response to the timing reference signal; and a radio receiver coupled to the receive timing circuit, wherein the radio receiver receives the radio signal carrying data from the data source in response to the receive timing signal. - View Dependent Claims (16, 17, 18, 19, 20, 21, 22, 23, 24)
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25. A system comprising:
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a first integrated circuit and a second integrated circuit; a wired interconnect structure coupled to the first and second integrated circuits; and a clock circuit coupled to the wired interconnect structure, the clock circuit transmitting a timing reference signal on the wired interconnect structure;
whereinthe first integrated circuit includes; a data source; a timing reference signal input adapted to receive the timing reference signal via the wired interconnect structure; a transmit timing circuit which produces a transmit timing signal in response to the timing reference signal; and a radio transmitter coupled to the transmit timing circuit and the data source which transmits a radio signal carrying data from the data source in response to the transmit timing signal; logic which executes a synchronization process to set timing for the transmit timing signal for the radio transmitter, the synchronization process including communication of a control signal related to the synchronization process via a wired interconnect structure with the second integrated circuit; and the second integrated circuit includes; a timing reference signal input adapted to receive the timing reference signal via the wired interconnect structure; a receive timing circuit which produces a receive timing signal in response to the timing reference signal; and a radio receiver coupled to the receive timing circuit, wherein the radio receiver receives the radio signal carrying data from the data source in response to the receive timing signal; and circuitry responsive to the synchronization process to adjust timing of the receive timing signal to coordinate communication between the first and second integrated circuits. - View Dependent Claims (26, 27)
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28. A system comprising:
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a first integrated circuit and a second integrated circuit; a wired interconnect structure coupled to the first and second integrated circuits; and a clock circuit coupled to the wired interconnect structure, the clock circuit transmitting a timing reference signal on the wired interconnect structure;
whereinthe first integrated circuit includes; a data source; a timing reference signal input adapted to receive the timing reference signal via the wired interconnect structure; a transmit timing circuit which produces a transmit timing signal in response to the timing reference signal; and a radio transmitter coupled to the transmit timing circuit and the data source which transmits a radio signal carrying data from the data source in response to the transmit timing signal; and the second integrated circuit includes; a timing reference signal input adapted to receive the timing reference signal via the wired interconnect structure; a receive timing circuit which produces a receive timing signal in response to the timing reference signal; and a radio receiver coupled to the receive timing circuit, wherein the radio receiver receives the radio signal carrying data from the data source in response to the receive timing signal;
includingcircuitry to adjust the timing of the transmit timing signal on the first integrated circuit, including; a phase locked loop which produces a phase locked clock signal in response to the timing reference signal, a mixer which provides a source for a plurality of phase shifted copies of the phase locked clock signal, and selection circuitry to select one of the plurality of phase shifted copies in response to a control parameter.
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29. A system comprising:
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a first integrated circuit and a second integrated circuit; a wired interconnect structure coupled to the first and second integrated circuits; and a clock circuit coupled to the wired interconnect structure, the clock circuit transmitting a timing reference signal on the wired interconnect structure;
whereinthe first integrated circuit includes; a data source; a timing reference signal input adapted to receive the timing reference signal via the wired interconnect structure; a transmit timing circuit which produces a transmit timing signal in response to the timing reference signal; and a radio transmitter coupled to the transmit timing circuit and the data source which transmits a radio signal carrying data from the data source in response to the transmit timing signal; and the second integrated circuit includes; a timing reference signal input adapted to receive the timing reference signal via the wired interconnect structure; a receive timing circuit which produces a receive timing signal in response to the timing reference signal; and a radio receiver coupled to the receive timing circuit, wherein the radio receiver receives the radio signal carrying data from the data source in response to the receive timing signal;
includingcircuitry to adjust the timing of the transmit timing signal on the first integrated circuit, including; a phase locked loop which produces a phase locked clock signal having a frequency of at least 1 GHz in response to the timing reference signal, a mixer which provides a source for a plurality of phase shifted copies of the phase locked clock signal, the plurality of phase shifted copies including at least 50 phase shifted copies, and selection circuitry to select one of the plurality of phase shifted copies in response to a control parameter.
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30. A system comprising:
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a first integrated circuit and a second integrated circuit; a wired interconnect structure coupled to the first and second integrated circuits; and a clock circuit coupled to the wired interconnect structure, the clock circuit transmitting a timing reference signal on the wired interconnect structure;
whereinthe first integrated circuit includes; a data source; a timing reference signal input adapted to receive the timing reference signal via the wired interconnect structure; a transmit timing circuit which produces a transmit timing signal in response to the timing reference signal; and a radio transmitter coupled to the transmit timing circuit and the data source which transmits a radio signal carrying data from the data source in response to the transmit timing signal; and the second integrated circuit includes; a timing reference signal input adapted to receive the timing reference signal via the wired interconnect structure; a receive timing circuit which produces a receive timing signal in response to the timing reference signal; and a radio receiver coupled to the receive timing circuit, wherein the radio receiver receives the radio signal carrying data from the data source in response to the receive timing signal;
includingcircuitry to adjust the timing of the receive timing signal on the second integrated circuit, including; a phase locked loop which produces a phase locked clock signal in response to the timing reference signal, a mixer which provides a source for a plurality of phase shifted copies of the phase locked clock signal, and selection circuitry to select one of the plurality of phase shifted copies in response to a control parameter.
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31. A system comprising:
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a first integrated circuit and a second integrated circuit; a wired interconnect structure coupled to the first and second integrated circuits; and a clock circuit coupled to the wired interconnect structure, the clock circuit transmitting a timing reference signal on the wired interconnect structure;
whereinthe first integrated circuit includes; a data source; a timing reference signal input adapted to receive the timing reference signal via the wired interconnect structure; a transmit timing circuit which produces a transmit timing signal in response to the timing reference signal; and a radio transmitter coupled to the transmit timing circuit and the data source which transmits a radio signal carrying data from the data source in response to the transmit timing signal; and the second integrated circuit includes; a timing reference signal input adapted to receive the timing reference signal via the wired interconnect structure; a receive timing circuit which produces a receive timing signal in response to the timing reference signal; and a radio receiver coupled to the receive timing circuit, wherein the radio receiver receives the radio signal carrying data from the data source in response to the receive timing signal;
includingcircuitry to adjust the timing of the receive timing signal on the second integrated circuit, including; a phase locked loop which produces a phase locked clock signal having a frequency of at least 1 GHz in response to the timing reference signal, a mixer which provides a source for a plurality of phase shifted copies of the phase locked clock signal, the plurality of phase shifted copies including at least 50 phase shifted copies, and selection circuitry to select one of the plurality of phase shifted copies in response to a control parameter.
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32. A system comprising:
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a first integrated circuit and a second integrated circuit mounted on a support structure and separated by a distance of less than 10 meters; a wired interconnect structure coupled to the first and second integrated circuits; and a clock circuit coupled to the wired interconnect structure transmitting a timing reference signal on the wired interconnect structure;
whereinthe first integrated circuit includes; a data source; a timing reference signal input adapted to receive the timing reference signal via the wired interconnect structure; a transmit timing circuit which produces a transmit timing signal in response to the timing reference signal, including circuitry to adjust the timing of the transmit timing signal by amounts of 10 picoseconds or less to synchronize communication between the first and second integrated circuits; logic coupled with the transmit timing circuit which executes a synchronization process to set the timing for the transmit timing signal for the radio transmitter, the synchronization process including communication of a control signal related to the synchronization process via the wired interconnect structure with the second integrated circuit; and a radio transmitter coupled to the transmit timing circuit and the data source which transmits an ultra-wide band impulse radio signal carrying data from the data source in response to the transmit timing signal; and the second integrated circuit includes; a timing reference signal input adapted to receive the timing reference signal via the wired interconnect structure; a receive timing circuit which produces a transmit timing signal in response to the timing reference signal; and a radio receiver coupled to the receive timing circuit which receives the ultra-wide band impulse radio signal carrying data from the data source in response to the receive timing signal.
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Specification