Apparatus and method for controlling power, clock, and reset during test and debug procedures for a plurality of processor/cores

• US 7,536,597 B2
• Filed: 04/26/2006
• Issued: 05/19/2009
• Est. Priority Date: 04/27/2005
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: McGowan, Robert A.
• Primary Examiner(s): Lohn; Joshua A
• Application Number:
  US11/411,683
• Publication Number:
  US 20060248395A1
• Time in Patent Office: 1,119 Days
• Field of Search: 714/30, 714/31
• US Class Current: 714/30
• CPC Class Codes: G06F 11/2236 to test CPU or processors
• CPC Class Codes: G06F 11/2242 in multi-processor systems, e.g. one processor becoming the test master G06F11/2736 takes precedence
• CPC Class Codes: G06F 11/261 by simulating additional hardware, e.g. fault simulation

Abstract

An interface unit is provided for use with a JTAG test and debug procedure involving a plurality of processor cores. The interface unit is provided with a logic unit that can translate test and debug commands into control signals. The control signals are applied to a power state machine coupled to a processor/core. The state of the power state machine can thereby be controlled and therefore the parameters of the associated processor/core, i.e., the power and clock parameters of the processor/core. In addition, the logic unit can generate control signals for activating switches, switches that controllably selective apply the TRST signal and the TMS signal to the TAP unit of the processor/core. This capability permits the TAP units of each processor/core to be synchronized.

Claims

1. An apparatus comprising:

a plurality of processor cores, wherein each processor core is coupled to a respective one power state machine of a plurality of power state machines, wherein each power state machine is configured to control power and clock parameters of the respective processor core, and wherein each processor core comprises a test access port (TAP); and

an interface unit coupled to the plurality of power state machines, wherein the interface unit comprises a TAP configured to receive test commands, and wherein the interface unit is configured to selectively provide control signals to the plurality of power state machines to force a parameter change in the respective processor cores in response to a received test command requesting the parameter change.

2. The apparatus of claim 1, wherein the interface unit is further configured to store current parameters of each processor core of the plurality of processor cores.

3. The apparatus of claim 1, wherein the interface unit is further configured to, in response to a received test command, communicate current parameters of at least one processor core to a test and debug unit using the TAP of the interface unit.

4. The apparatus of claim 1, wherein each power state machine is further configured to confirm to the interface unit that a requested parameter change is completed.

5. The apparatus of claim 1, further comprising:

a plurality of switch units, wherein each switch unit is coupled to the TAP of a respective one processor core of the plurality of processor cores, and wherein each switch unit is coupled to receive a test signal from a test and debug unit, and

wherein the interface unit is coupled to the plurality of switch units to selectively provide control signals to the plurality of switch units, and wherein the interface unit is further configured to, in response to a received test command, selectively provide control signals to at least one of the switch units to cause the at least one switch unit to apply the received test signal to the respective TAP.

6. The apparatus of claim 5, wherein the test signal is a JTAG test signal.

7. The apparatus of claim 5, wherein the test signal is one selected from a group consisting of a JTAG test reset signal (TRST) and a JTAG test mode select (TMS) signal.

8. The apparatus of claim 1, wherein the plurality of processor cores are on a same substrate.

9. method comprising:

receiving a test command in a test access port (TAP) of an interface unit coupled to a plurality of power state machines, wherein each power state machine is coupled to a respective one processor core of a plurality of processor cores to control power and clock parameters of the respective one processor core, wherein each processor core comprises a TAP, and wherein the test command requests a parameter change in at least one processor core of the plurality of processor cores; and

sending, by the interface unit, control signals to the power state machine coupled to the at least one processor core, wherein the parameter change is forced.

10. The method of claim 9, further comprising:

receiving, by the interface unit, confirmation from the power state machine that the parameter change is complete.

11. The method of claim 10, further comprising:

storing the changed parameters in the interface unit in response to the confirmation.

12. The method of claim 9, further comprising:

storing current parameters of each processor core in the interface unit.

13. The method of claim 9, further comprising:

sending, by the interface unit, current parameters of the at least one processor core to a test and debug unit responsive to a test command.

14. The method of claim 9, further comprising:

receiving a test signal from a test and debug unit at a switch unit coupled to the TAP of the at least one processor core; and

sending, by the interface unit in response to a test command, control signals to the switch unit to cause the switch unit to apply the test signal to the TAP.

15. The method of claim 14, wherein the test signal is one selected from a group consisting of a JTAG test reset signal (TRST) and a JTAG test mode select (TMS) signal.

16. An apparatus comprising:

a processor core comprising a processor test access port (TAP), wherein the processor TAP is operable to control testing of the processor core;

a power state machine controllably coupled to the processor core to change clock and power parameters of the processor core; and

an interface unit controllably coupled to the power state machine, wherein the interface unit comprises an interface TAP operable to receive test commands and the interface unit is operable to force a change to the clock and power parameters responsive to a test command received by the interface TAP.

17. The apparatus of claim 16, wherein the interface unit is controllably coupled to the processor TAP to cause a test signal received from a test and debug unit to be applied to the processor TAP in response to a test command received by the interface TAP.

18. The apparatus of claim 17, wherein the test signal is one selected from a group consisting of a JTAG test reset signal (TRST) and a JTAG test mode select (TMS) signal.

19. A method for testing a processor core controllably coupled to a power state machine, the method comprising:

receiving test commands for testing the processor core at a processor test access port (TAP) comprised in the processor core;

receiving test commands to request changes to power and clock parameters of the processor core at an interface TAP of an interface unit controllably coupled to the power state machine; and

forcing a change to the parameters in response to a test command received by the interface TAP.

20. The method of claim 19, further comprising:

applying a test signal received from a test and debug unit to the processor TAP in response to a test command received by the interface TAP, wherein the interface unit is controllably coupled to the processor tap to cause the application of the test signal.