Bi-directional transistor with by-pass path and method therefor

• US 7,537,970 B2
• Filed: 03/06/2006
• Issued: 05/26/2009
• Est. Priority Date: 03/06/2006
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Inventors: Robb, Stephen P., Robb, Francine Y.
• Primary Examiner(s): PHAM, THANHHA S
• Application Number:
  US11/367,626
• Publication Number:
  US 20070205431A1
• Time in Patent Office: 1,177 Days
• Field of Search: 438133-135, 438138-139, 438/141, 438/237, 438/275, 438/327, 257/E29.215
• US Class Current: 438/134
• CPC Class Codes: H01L 21/823487 with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface with a current flow parallel to the substrate surface H01L21/823431
• CPC Class Codes: H01L 21/823885 with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface with a current flow parallel to the substrate surface H01L21/823821
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 27/0922 Combination of complementary transistors having a different structure, e.g. stacked CMOS, high-voltage and low-voltage CMOS
• CPC Class Codes: H03K 17/063 in field-effect transistor switches
• CPC Class Codes: H03K 17/687 the devices being field-effect transistors
• CPC Class Codes: H03K 2217/0018 Special modifications or use of the back gate voltage of a FET

Abstract

In one embodiment, a transistor is formed to have a first current flow path to selectively conduct current in both directions through the transistor and to have a second current flow path to selectively conduct current in one direction.

Claims

1. A method of forming a bi-directional transistor comprising:

forming a first MOS transistor on a semiconductor substrate of a first conductivity type, the first MOS transistor having a first current carrying electrode and a second current carrying electrode;

forming a body region of the first MOS transistor on a surface of the semiconductor substrate and isolated from a first current carrying electrode region of the first MOS transistor by a first P-N junction and isolated from a second current carrying electrode region of the first MOS transistor by a second P-N junction;

forming a second MOS transistor configured to selectively couple the body region of the first MOS transistor to the first current carrying electrode of the first MOS transistor; and

forming a third MOS transistor on a surface of the semiconductor substrate and coupled to form a current flow path in parallel with the first MOS transistor.

2. The method of claim 1 further including forming the second MOS transistor electrically coupled between the body region of the first MOS transistor and the second current carrying electrode region of the first MOS transistor.

3. The method of claim 1 wherein the first MOS transistor is a vertical transistor and the second MOS transistor is a lateral MOS transistor formed on the semiconductor substrate.

4. The method of claim 1 further including a fourth MOS transistor configured to selectively couple the body region of the first MOS transistor to the second current carrying electrode of the first MOS transistor.

5. A method of forming a bi-directional transistor comprising:

forming a first MOS transistor on a semiconductor substrate of a first conductivity type, the first MOS transistor having a first current carrying electrode and a second current carrying electrode;

forming a body region of the first MOS transistor on a surface of the semiconductor substrate and isolated from a first current carrying electrode region of the first MOS transistor by a first P-N junction and isolated from a second current carrying electrode region of the first MOS transistor by a second P-N junction;

forming a third P-N junction on the surface of the semiconductor substrate and spaced apart from the first P-N junction wherein the third P-N junction is not a portion of the first transistor, the third P-N junction having a first electrode and a second electrode wherein the first electrode is coupled to the first current carrying electrode of the first transistor; and

forming a fourth P-N junction on the surface of the semiconductor substrate and spaced apart from the first P-N junction and the third P-N junction wherein the fourth P-N junction is not a portion of the first transistor, the fourth P-N junction having a first electrode and a second electrode wherein the first electrode is coupled to the second current carrying electrode of the first transistor and wherein the second electrode of the fourth P-N junction is coupled to the second electrode of the third P-N junction.