Method for manufacturing a CMOS image sensor

• US 7,537,999 B2
• Filed: 12/24/2003
• Issued: 05/26/2009
• Est. Priority Date: 09/23/2003
• Status: Active Grant

• Current Assignee: DB HiTek Co., Ltd.
• Original Assignee: DONGBU ELECTRONICS CO., LTD. (DB HiTek Co., Ltd.)
• Inventors: Han, Chang Hun
• Primary Examiner(s): Smith, Matthew
• Assistant Examiner(s): Jefferson, Quovaunda
• Application Number:
  US10/746,702
• Publication Number:
  US 20050064665A1
• Time in Patent Office: 1,980 Days
• Field of Search: 438/373, 438/57, 438/60, 438/289, 438/48, 438/199, 438/59, 438/63, 438/73, 438/75, 438/90, 438/197, 438/200, 438229-232, 438/237, 438/286, 438/299, 438/FOR.136, 438/FOR.139, 438/FOR.149, 438/FOR.213, 257/E21.532, 257/E21.04, 257/E21.085, 257/E27.133, 257/E27.131
• US Class Current: 438/286
• CPC Class Codes: H01L 27/14603 Special geometry or disposition of pixel-elements, address-lines or gate-electrodes
• CPC Class Codes: H01L 27/14643 Photodiode arrays; MOS imagers
• CPC Class Codes: H01L 27/14689 MOS based technologies
• CPC Class Codes: H01L 31/035272 characterised by at least one potential jump barrier or surface barrier

Abstract

A method for manufacturing structures of a CMOS image sensor. The method comprises the steps of depositing a gate insulating layer and a conductive layer on a semiconductor substrate; depositing an ion implantation barrier layer on the conductive layer; patterning the deposited gate insulating layer, conductive layer and ion implantation barrier layer to form a patterned, composite gate insulating layer, gate electrode and ion implantation barrier structure; forming a second photosensitive layer pattern to define a photodiode region; and implanting low-concentration dopant ions into the substrate using the second photosensitive layer pattern as an ion implantation mask to form a low-concentration dopant region within the photodiode region.

Claims

1. A method for manufacturing complementary metal oxide semiconductor (CMOS) image sensor structures, comprising the steps of:

(a) forming a gate insulating layer, a conductive layer and an ion implantation barrier layer on a semiconductor substrate;

(b) patterning said ion implantation barrier layer, said conductive layer, and said gate insulating layer;

(c) forming a photoresist layer on said patterned ion implantation barrier layer, said conductive layer, and said gate insulating layer and patterning said photoresist layer to define a photodiode region in said substrate; and

(d) implanting a low concentration of dopant ions into said photodiode region using said photoresist layer pattern and said patterned ion implantation barrier layer as an ion implantation mask to form a low-concentration dopant region of a photodiode,

wherein said ion implantation barrier layer comprises an oxide layer and/or a nitride layer,

wherein one end of the photoresist layer pattern is on said ion implantation barrier layer and another end of the photoresist layer pattern is not on said photodiode region,

wherein the ion implantation barrier layer prevents the low-concentration dopant region from overlapping with a lower region of the gate electrode, and

wherein a depth of said low-concentration dopant region is larger than a height of said conductive layer, but the depth of said low-concentration dopant region is smaller than a sum of the height of said conductive layer and a height of said ion implantation barrier layer.

2. The method as claimed in claim 1, wherein said conductive layer has a thickness between 1500 and 2600 Å

.

3. The method as claimed in claim 1, wherein said low-concentration dopant region has a depth between 2500 and 3500 Å

.

4. The method as claimed in claim 1, wherein said ion implantation barrier layer comprises a TEOS (Tetra Ethyl Ortho Silicate) based insulating layer.

5. The method as claimed in claim 1, further comprising a step of implanting a high concentration of dopant ions into the low-concentration dopant region after implanting said low concentration of dopant ions, so as to reduce a current generated by said image sensor.

6. The method as claimed in claim 1, further comprising forming a p-type epitaxial layer on or in said substrate before said gate insulating layer is formed on said substrate.

7. The method as claimed in claim 1, wherein the step of forming said gate insulating layer, said conductive layer and said ion implantation barrier layer comprises blanket depositing said conductive layer and said ion implantation barrier layer onto said gate insulating layer to form a composite gate electrode layer.

8. The method as claimed in claim 7, wherein the step of patterning said ion implantation barrier layer, said conductive layer, and said gate insulating layer comprises depositing, selectively irradiating and developing a second photoresist on said composite gate electrode layer, then sequentially etching said ion implantation barrier layer, said conductive layer and said gate insulating layer to form a gate electrode.

9. The method as claimed in claim 8, wherein the step of patterning said photoresist Layer prevents ions from being implanted into a source/drain terminal region of a CMOS transistor comprising said gate electrode.

10. The method as claimed in claim 9, further comprising the step of forming said source/drain terminal region of said CMOS transistor.

11. The method as claimed in claim 1, further comprising the step of removing said. ion implantation barrier layer after the step of implanting said low concentration of dopant ions into said photodiode region.

12. The method as claimed in claim 1, further comprising the step of implanting a high concentration of ions into said photodiode region.

13. The method as claimed in claim 1, wherein patterning the photoresist layer comprises forming one end of the photoresist layer pattern spaced apart from the corresponding end of the patterned conductive layer by at least an error of the radiation source.

14. The method as claimed in claim 1, wherein patterning the photoresist layer comprising forming the one end of the photoresist layer pattern spaced apart from the other end of the patterened gate electrode by 0.15 μ

m or more.

15. The method as claimed in claim 1, wherein the photoresist layer pattern inhibits ions from being implanted into a source/drain terminal region of a CMOS transistor comprising the patterned conductive layer.

16. The method as claimed in claim 1, wherein the photoresist layer pattern prevents ions from being implanted into a source/drain terminal region of a CMOS transistor comprising the patterned conductive layer.

17. The method as claimed in claim 16, further comprising implanting low-concentration dopant ions into a drain region of the CMOS transistor to form a LDD structure.

18. The method as claimed in claim 16, further comprising forming a source/drain terminal in the source/drain terminal region of the CMOS transistor.

19. The method as claimed in claim 1, wherein said ion implantation barrier layer has a thickness between 1100 and 1300 Å

.

20. The method as claimed in claim 1, wherein patterning the photoresist layer exposes the entire photodiode region.

21. The method as claimed in claim 20, wherein patterning the photoresist layer further exposes the isolating layer.