Low temperature method for fabricating high-aspect ratio vias and devices fabricated by said method

• US 7,538,032 B2
• Filed: 06/23/2005
• Issued: 05/26/2009
• Est. Priority Date: 06/23/2005
• Status: Active Grant

• Current Assignee: Teledyne Scientific & Imaging, LLC (Teledyne Technologies Incorporated)
• Original Assignee: Teledyne Scientific & Imaging, LLC (Teledyne Technologies Incorporated)
• Inventors: Stupar, Philip A., Yao, Zhimin J., White, John, Tench, Morgan, Borwick, Robert L., Tsai, Chailun, Warren, Les, DeNatale, Jeffrey F., Garrett, Kathleen
• Primary Examiner(s): Kebede, Brook
• Application Number:
  US11/167,014
• Publication Number:
  US 20060292866A1
• Time in Patent Office: 1,433 Days
• Field of Search: 438/638, 438/641, 438/643, 438/644, 438/678, 438/681, 438/686, 438/687, 438/667, 438/668, 257/E23.067, 257/E21.577, 257/E21.578
• US Class Current: 438/667
• CPC Class Codes: H01L 21/288 from a liquid, e.g. electrolytic deposition
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

Embodiments of the present invention are directed to a process for forming small diameter vias at low temperatures. In preferred embodiments, through-substrate vias are fabricated by forming a through-substrate via; and depositing conductive material into the via by means of a flowing solution plating technique, wherein the conductive material releases a gas that pushes the conductive material through the via to facilitate plating the via with the conductive material. In preferred embodiments, the fabrication of the substrate is conducted at low temperatures.

Claims

1. A process for fabricating a through-wafer via through a semiconductor wafer on which active circuitry has been fabricated, the wafer having a first surface and a second surface, comprising:

forming a through-wafer via hole into a semiconductor wafer on which active circuitry has been fabricated;

forming an isolation material directly onto the wafer and onto the interior semiconductor walls of said through-wafer via hole, said isolation material being electrically insulating, continuous and substantially conformal;

preparing the isolation material for receiving a conductive material such that the conductive material will react with the isolation material to plate the via; and

depositing conductive material into the via hole over said isolation material such that it is electrically continuous across the length of said via hole, said conductive material deposited by means of an electroless flowing solution plating process.

2. A process as claimed in claim 1, wherein forming the through-substrate via, forming isolation material, and depositing conductive material are performed at a low temperature range.

3. A process as claimed in claim 2, wherein said low temperature range is less than 100°

C.

4. A process as claimed in claim 2, wherein said low temperature is less than 400°

C.

5. A process as claimed in claim 1, wherein said isolation material is formed onto said substrate via by a process selected from the group consisting of vapor-deposition of organic materials, atomic layer deposition, plasma enhanced chemical vapor deposition, and polymer passivation coatings derived from substrate etch processing.

6. A process as claimed in claim 1, wherein the isolation material is prepared by activating it with a seed layer which reacts with the conductive material and thereby promotes said electroless deposition.

7. A process as claimed in claim 1, further comprising:

forming a plurality of vias into the substrate; and

plating said plurality of vias by said electroless flowing solution plating process.

8. A process as claimed in claim 1, wherein the depth of the vias is greater than 100 μ

m.

9. A process as claimed in claim 1, wherein said through-substrate via is formed by:

etching a first cavity into the first surface of the substrate with a first diameter; and

etching a second cavity into the second surface of the substrate with a second diameter, wherein the first and second cavities form a single continuous aperture through the substrate.

10. A process as claimed in claim 9, wherein said first and second cavities extend to depths in the range of 20 μ

m-200 μ

m and 100 μ

m-350 μ

m, respectively.

11. A process as claimed in claim 10, wherein said first and second diameters are in the range of 2 μ

m-8 μ

m and 6 μ

m-25 μ

m, respectively.

12. A process as claimed in claim 9, wherein said first and second cavities are etched by a deep reactive ion etching process.

13. A process as claimed in claim 1, wherein the reaction to deposit the conductive material releases a gas that pushes the conductive material solution through the via to facilitate plating the via with the conductive material.

14. A process as claimed in claim 1, wherein a solution flow is generated by mechanical agitation to facilitate plating with the conductive material.

15. A process as claimed in claim 1, wherein the isolation material is an organic isolation material which is prepared by activating it with a seed layer that reacts with the conductive material, said seed layer being deposited at low temperatures by atomic layer deposition or chemical vapor deposition.

16. The process of claim 1, wherein said organic isolation material is parylene.

17. A process for fabricating a through-substrate via, the substrate having a first surface and a second surface, comprising:

forming a through-substrate via hole into the substrate;

forming an isolation material onto the substrate and on the interior walls of said via hole, said isolation material being electrically insulating, continuous and substantially conformal;

preparing the isolation material for receiving a conductive material;

depositing conductive material into the via hole by means of a flowing solution plating technique such that it is electrically continuous across the length of said via hole, and such that the conductive material reacts with the isolation material to plate the via;

wherein the isolation material is parylene; and

the isolation material is prepared by activating it with a plasma.

18. A process for fabricating a through-substrate via, the substrate having a first surface and a second surface, comprising:

forming a through-substrate via hole into the substrate;

forming an isolation material onto the substrate and on the interior walls of said via hole, said isolation material being electrically insulating, continuous and substantially conformal;

preparing the isolation material for receiving a conductive material;

depositing conductive material into the via hole by means of a flowing solution plating technique such that it is electrically continuous across the length of said via hole, and such that the conductive material reacts with the isolation material to plate the via;

wherein the isolation material is prepared by activating it with a seed layer which reacts with the conductive material; and

wherein the seed layer is applied by;

absorbing tin onto the isolation material by bathing the substrate in a solution of stannous chloride and hydrochloric acid; and

bathing the substrate in a solution of palladium chloride and hydrochloric acid to deposit palladium on the substrate'"'"'s surface.

19. A process for fabricating a through-substrate via, the substrate having a first surface and a second surface, comprising:

forming a through-substrate via hole into the substrate;

forming an isolation material onto the substrate and on the interior walls of said via hole, said isolation material being electrically insulating, continuous and substantially conformal;

preparing the isolation material for receiving a conductive material;

depositing conductive material into the via hole by means of a flowing solution plating technique such that it is electrically continuous across the length of said via hole, and such that the conductive material reacts with the isolation material to plate the via;

wherein the isolation material is prepared by activating it with a seed layer which reacts with the conductive material; and

wherein the seed layer is applied by;

bathing the substrate in a solution containing a metal acetate such that the vias are coated with the metal acetate;

heating the solution such that the metal acetate solution forms a thin metal layer on the interior surfaces of the vias.

20. A process for fabricating a through-wafer via through a semiconductor wafer, said wafer having a first surface and a second surface and having active circuitry fabricated on said first surface, comprising:

etching a first cavity having a first diameter into the first surface of said wafer; and

etching a second cavity having a second diameter into the second surface of said wafer, wherein the first and second cavities form a single continuous aperture through the wafer, thereby forming a through-wafer via hole, said cavities arranged such that said first diameter is less than said second diameter so as to reduce the area of said first surface occupied by said via;

depositing an isolation material directly onto the wafer and onto the interior semiconductor walls of said through-wafer via hole, said isolation material being electrically insulating, continuous and substantially conformal; and

depositing conductive material into the via hole over said isolation material such that it is electrically continuous across the length of said via hole.