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Low temperature method for fabricating high-aspect ratio vias and devices fabricated by said method

  • US 7,538,032 B2
  • Filed: 06/23/2005
  • Issued: 05/26/2009
  • Est. Priority Date: 06/23/2005
  • Status: Active Grant
First Claim
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1. A process for fabricating a through-wafer via through a semiconductor wafer on which active circuitry has been fabricated, the wafer having a first surface and a second surface, comprising:

  • forming a through-wafer via hole into a semiconductor wafer on which active circuitry has been fabricated;

    forming an isolation material directly onto the wafer and onto the interior semiconductor walls of said through-wafer via hole, said isolation material being electrically insulating, continuous and substantially conformal;

    preparing the isolation material for receiving a conductive material such that the conductive material will react with the isolation material to plate the via; and

    depositing conductive material into the via hole over said isolation material such that it is electrically continuous across the length of said via hole, said conductive material deposited by means of an electroless flowing solution plating process.

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