Graphics processing system with enhanced memory controller

• US 7,538,772 B1
• Filed: 11/28/2000
• Issued: 05/26/2009
• Est. Priority Date: 08/23/2000
• Status: Active Grant

• Current Assignee: Nintendo Company Limited
• Original Assignee: Nintendo Company Limited
• Inventors: Yeung, Winnie W., Cheng, Howard, Fouladi, Farhad
• Primary Examiner(s): Tung; Kee M
• Assistant Examiner(s): RICHER, JONI
• Application Number:
  US09/726,220
• Time in Patent Office: 3,101 Days
• Field of Search: 711/154, 711/158, 711/167, 711/137, 711/113, 711/106, 711/100, 711/163, 711/151, 711/156, 711/140, 711/141, 711/157, 711/105, 711/5, 365/222, 345/519, 345/542, 345/422, 345/531, 345/570, 345/535, 345/530, 345/536, 345/558, 345/559, 709/235, 710/240, 710/100, 710/315, 710/5, 710/310, 710/105, 710/117, 710/40
• US Class Current: 345/535
• CPC Class Codes: G06F 13/1605 based on arbitration arbitration in handling access to a common bus or bus system G06F13/36
• CPC Class Codes: G06T 1/60 Memory management

Abstract

A graphics system including a custom graphics and audio processor produces exciting 2D and 3D graphics and surround sound. The system includes a graphics and audio processor including a 3D graphics pipeline and an audio digital signal processor. A memory controller performs a wide range of memory control related functions including arbitrating between various competing resources seeking access to main memory, handling memory latency and bandwidth requirements of the resources requesting memory access, buffering writes to reduce bus turn around, refreshing main memory, and protecting main memory using programmable registers. The memory controller minimizes memory read/write switching using a “global” write queue which queues write requests from various diverse competing resources. In this fashion, multiple competing resources for memory writes are combined into one resource from which write requests are obtained. Memory coherency issues are addressed both within a single resource that has both read and write capabilities and among different resources by efficiently flushing write buffers associated with a resource.

Claims

1. In a graphics system including a main processor and a graphics processing system for generating graphics images on a display in cooperation with said main processor, and a main memory, said system including a plurality of resources requesting access to said main memory, a memory controller comprising:

a plurality of buffer memories, each of said buffer memories being operatively coupled to one of said plurality of resources requesting access to said main memory for storing information indicative of a request for main memory access;

a multiple resource buffer memory coupled to said plurality of buffer memories for storing requests for main memory access from each of said plurality of resources; and

a control circuit for controlling the transfer of information from said plurality of buffer memories to said multiple resource buffer memory, wherein said control circuit is operable to control the transfer of information from said plurality of buffer memories to said multiple resource buffer memory to reduce the frequency of switching from main memory write operations to main memory read operations,

wherein said plurality of buffer memories and said multiple resource buffer memory are write request queues,

wherein a resource that is writing to main memory generates a flush signal for initiating flushing of that resource'"'"'s write request queue, and

wherein said memory controller further includes a flush acknowledge handshake signal generating circuit that generates a flush acknowledge handshake signal to thereby indicate to competing resources that data written to main memory is actually stored in main memory rather than in an associated resource'"'"'s buffer.

2. A memory controller according to claim 1, wherein said control circuit is operable to control the rate at which write requests are coupled to the multiple resource buffer memory from the plurality of buffer memories.

3. A memory controller according to claim 1, further including a plurality of main memory read queues, each read queue being operatively coupled to a resource requesting to read information from said main memory.

4. A memory controller according to claim 1, wherein said control circuit includes arbitration circuitry for arbitrating requests for access to said main memory.

5. A memory controller according to claim 4, wherein said arbitration circuitry is operable to control the frequency with which the requesting resources are enabled to participate in the arbitrating for main memory access.

6. A memory controller according to claim 1, further including a memory access control register associated with one of said resources, wherein said control circuit includes arbitration circuitry responsive to the contents of said memory access control register for determining the frequency that said resource is permitted to participate in the arbitrating for main memory access.

7. A memory controller according to claim 1, further including a set of control registers, said control registers being programmable by said main processor.

8. A memory controller according to claim 7, wherein said control circuitry is operable to arbitrate between said resources for granting requests for main memory access, wherein said control registers include a plurality of memory bandwidth control registers which are accessed by said control circuitry in determining which resource will be granted main memory access.

9. A memory controller according to claim 8, wherein each of said memory bandwidth control registers is respectively associated with a resource seeking main memory access.

10. A memory controller according to claim 7, wherein said control registers include at least one register associated with a main memory access requesting resource for storing data for said requesting resource indicative of at least one of memory usage and memory bandwidth for that resource.

11. In a graphics system including a main processor and a graphics processing system for generating graphics images on a display in cooperation with said main processor, and a main memory, said system including a plurality of resources requesting access to said main memory, a memory controller comprising:

a plurality of buffer memories, each of said buffer memories being operatively coupled to one of said plurality of resources requesting access to said main memory for storing information indicative of a request for main memory access;

a multiple resource buffer memory coupled to said plurality of buffer memories for storing requests for main memory access from each of said plurality of resources; and

a control circuit for controlling the transfer of information from said plurality of buffer memories to said multiple resource buffer memory, wherein said control circuit is operable to control the transfer of information from said plurality of buffer memories to said multiple resource buffer memory to reduce the frequency of switching from main memory write operations to main memory read operations; and

at least one register associated with a main memory access requesting resource for storing data for said requesting resource indicative of wasted memory cycles due to granting main memory access to that resource.

12. In an information processing system including a main processor, a main memory, and at least a first and a second resource competing with said main processor for access to said main memory, a memory controller comprising:

a main processor related interface including a main processor read request queue and a main processor write request queue;

a first resource related interface including at least one of a first resource read request queue and a first resource write request queue;

a second resource related interface including at least one of a second resource read request queue and a second resource write request queue;

a multiple resource write request queue for receiving requests for writing to said main memory; and

a memory access control circuit for granting access to said main memory, said memory access control circuit being coupled to receive read requests from each of said read request queues and for receiving write requests from said multiple resource write request queues

wherein a resource that is writing to main memory generates a flush signal for initiating flushing of that resource'"'"'s write request queue, and

wherein said memory controller further includes a flush acknowledge handshake signal generating circuit to generate a flush acknowledge handshake signal and thereby indicate to competing resources that data written to main memory is actually stored in main memory rather than in an associated resource buffer.

13. A memory controller according to claim 12, wherein said memory access control circuit is operable to control the transfer of information from said main processor write request queue, said first resource write request queue and said second resource write request queue to said multiple resource write request queue to thereby reduce the frequency of switching from main memory write operations to main memory read operations.

14. A memory controller according to claim 12, wherein said memory access control circuitry is operable to arbitrate among resources competing for memory access to said main memory and to control the frequency with which requesting resources are enabled to participate in the arbitration.

15. A memory controller according to claim 12, further including a memory access control register associated with one of said resources, wherein said memory access control circuit includes arbitration circuitry responsive to the contents of said memory access control register for determining the frequency that said resource is permitted to participate in main memory access arbitration.

16. A memory controller according to claim 12, further including a set of control registers, said control registers being programmable by said main processor.

17. A memory controller according to claim 16, wherein said memory access control circuit is operable to arbitrate between said resources for granting requests for access to said main memory, wherein said control registers include a plurality of memory bandwidth control registers which are accessed by said memory access control circuit in determining which resource will be granted main memory access.

18. A memory controller according to claim 17, wherein each of said memory bandwidth control registers is respectively associated with a resource requesting main memory access.

19. A memory controller according to claim 16, wherein said control registers include at least one performance related register associated with a main memory access requesting resource for storing data for said requesting resource indicative of at least one of memory usage and memory bandwidth for that resource.

20. In an information processing system including a main processor, a main memory, and at least a first and a second resource competing with said main processor for access to said main memory, a memory controller comprising:

a main processor related interface including a main processor read request queue and a main processor write request queue;

a first resource related interface including at least one of a first resource read request queue and a first resource write request queue;

a second resource related interface including at least one of a second resource read request queue and a second resource write request queue;

a multiple resource write request queue for receiving requests for writing to said main memory;

a memory access control circuit for granting access to said main memory, said memory access control circuit being coupled to receive read requests from each of said read request queues and for receiving write requests from said multiple resource write request queue; and

at least one performance related register associated with a main memory access requesting resource for storing data for said requesting resource indicative of wasted memory cycles due to granting main memory access to that resource.

21. In an information system including a main processor, a main memory, and at least a first and a second resource competing with said main processor for access to said main memory, a method of controlling access to said main memory comprising the steps of:

storing requests for main memory access from a first resource in a first resource request queue;

storing requests for main memory access from a second resource in a second resource request queue;

delaying forwarding requests for main memory access to a memory access control circuit to reduce the frequency of switching between memory read states and memory write states;

granting requests for main memory access by said memory access control circuit;

writing data by a resource to main memory;

generating a buffer flush signal for initiating flushing of that resource'"'"'s write request queue; and

generating a flush acknowledge handshake signal to competing resources that data written to main memory is actually stored in main memory rather than in an associated resource'"'"'s buffer.

22. A method according to claim 21, wherein said step of delaying includes the step of storing requests in a multiple resource write queue.

23. A method according to claim 21, further including the step of storing requests for main memory access by said main processor in a main processor request queue.

24. A method according to claim 21, wherein said step of granting requests for main memory access includes the step of arbitrating among competing resources and further including the step of controlling the frequency with which requesting resources are enabled to participate in main memory access arbitration.

25. A method according to claim 24, wherein the step of controlling the frequency includes the step of accessing contents of a memory access control register associated with a resource for determining the frequency that said resource is permitted to participate in main memory access arbitration.

26. A method according to claim 21, further including the step of controlling main memory access by programming at least one of a set of control registers in said memory controller by said main processor.

27. A method according to claim 21, wherein said step of granting main memory access includes the step of arbitrating between said resources for granting requests for main memory access, and further including the step of accessing a plurality of memory bandwidth control registers and determining which resource will be granted main memory access in part based upon the contents of said memory bandwidth control registers.

28. A method according to claim 27, further including the step of associating each of said memory bandwidth control registers with a resource seeking main memory access.

29. A method according to claim 21, further including the step of storing data relating to a requesting resource indicative of at least one of memory usage and memory bandwidth for that resource.

30. A method according to claim 21, wherein the step of granting requests includes the step of fulfilling requests for main memory access in the order requested.

31. In an information system including a main processor, a main memory, and at least a first and a second resource competing with said main processor for access to said main memory, a method of controlling access to said main memory comprising the steps of:

storing requests for main memory access from a first resource in a first resource request queue;

storing requests for main memory access from a second resource in a second resource request queue;

delaying forwarding requests for main memory access to a memory access control circuit to reduce the frequency of switching between memory read states and memory write states;

granting requests for main memory access by said memory access control circuit; and

storing data for a requesting resource indicative of wasted memory cycles due to granting main memory access to that resource.

32. In an information system including a main processor, a main memory, and at least a first and a second resource competing with said main processor for access to said main memory, a method of controlling access to said main memory comprising the steps of:

storing requests for writing to main memory from a first resource in a first resource write request queue;

writing to main memory by said first resource;

generating a write queue flush signal by said first resource to initiate copying information in said first resource write request queue to main memory;

flushing said first resource write request queue; and

generating a flush acknowledge handshake signal to competing resources that data written to main memory is actually stored in main memory rather than in said first resource write queue.

33. A method according to claim 32, further including the steps of

storing requests for writing to main memory from a second resource in a second resource write request queue;

delaying forwarding requests for memory access to a memory access control circuit to reduce the frequency of switching between main memory read states and main memory write states; and

granting requests for main memory access by said memory access control circuit.

34. A method according to claim 33, wherein said step of delaying includes the step of storing requests in a multiple resource write queue.

35. A method according to claim 32, further including the step of storing requests for main memory access by said main processor in a main processor request queue.

36. A method according to claim 32, further including the steps of arbitrating requests for main memory access among competing resources and controlling the frequency with which requesting resources are enabled to participate in main memory access arbitration.

37. A method according to claim 36, wherein the step of controlling the frequency includes the step of accessing the contents of a memory access control register associated with a resource for determining the frequency that said resource is permitted to participate in main memory access arbitration.

38. A method according to claim 32, further including the step of controlling main memory access by programming at least one of a set of control registers in said memory controller by said main processor.

39. A method according to claim 32, further including the steps of arbitrating main memory access requests between said resources by accessing a plurality of memory bandwidth control registers and determining which resource will be granted main memory access in part based upon the contents of said memory bandwidth control registers.

40. A method according to claim 39, further including the step of associating each of said memory bandwidth control registers with a resource seeking main memory access.

41. A method according to claim 32, further including the step of storing data relating to a requesting resource indicative of at least one of memory usage and memory bandwidth for that resource.

42. A method according to claim 32, further including the step of fulfilling requests for main memory access in the order requested.

43. In an information system including a main processor, a main memory, and at least a first and a second resource competing with said main processor for access to said main memory, a method of controlling access to said main memory comprising the steps of:

storing requests for writing to main memory from a first resource in a first resource write request queue;

writing to main memory by said first resource;

generating a write queue flush signal by said first resource to initiate copying information in said first resource write request queue to main memory;

flushing said first resource write request queue;

storing requests for reading from main memory from a second resource in a second resource read request queue;

comparing the main memory address associated with the read request with the addresses stored in at least one write queue; and

flushing said at least one write queue if there is a match between the main memory address associated with the read request and any of the addresses stored in said at least one write queue.

44. In an information system including a main processor, a main memory, and at least a first and a second resource competing with said main processor for access to said main memory, a method of controlling access to said main memory comprising the steps of:

storing requests for writing to main memory from a first resource in a first resource write request queue;

writing to main memory by said first resource;

generating a write queue flush signal by said first resource to initiate copying information in said first resource write request queue to main memory;

flushing said first resource write request queue; and

storing data for a requesting resource indicative of wasted memory cycles due to granting main memory access to that resource.

45. In a graphics system including a main processor and a graphics processing system for generating graphics images on a display in cooperation with said main processor, and a main memory, said system including a plurality of resources requesting access to said main memory, a memory controller comprising:

a plurality of buffer memories, two or more of said buffer memories being operatively coupled to a different respective one of said plurality of resources requesting access to said main memory and storing information indicative of a request for main memory access from that one of said plurality of resources;

a multiple resource buffer memory coupled to said plurality of buffer memories; and

a control circuit for controlling the transfer of requests from said plurality of buffer memories to said multiple resource buffer memory, wherein said control circuit is operable to control the transfer of the requests from said plurality of buffer memories to said multiple resource buffer memory to reduce the frequency of switching from main memory write operations to main memory read operations,

wherein said plurality of buffer memories and said multiple resource buffer memory are write request queues,

wherein a resource that is writing to main memory generates a flush signal for initiating flushing of that resource'"'"'s write request queue, and

wherein a flush acknowledge handshake signal indicates to competing resources that data written to main memory is actually stored in main memory rather than in an associated resource'"'"'s buffer.