Receptacle circuit interrupting devices providing an end of life test controlled by test button

• US 7,538,993 B2
• Filed: 10/24/2006
• Issued: 05/26/2009
• Est. Priority Date: 02/25/2005
• Status: Expired due to Fees

• Current Assignee: Huadao Huang
• Original Assignee: Huadao Huang
• Inventors: Huang, Huadao, Huayang, Lu
• Primary Examiner(s): Barrera; Ramon M
• Application Number:
  US11/585,170
• Publication Number:
  US 20070041134A1
• Time in Patent Office: 945 Days
• Field of Search: 335/6, 335/18, 361 42- 50
• US Class Current: 361/42
• CPC Class Codes: H01H 2071/044 Monitoring, detection or measuring systems to establish the end of life of the switching device, can also contain other on-line monitoring systems, e.g. for detecting mechanical failures
• CPC Class Codes: H01H 71/123 using a solid-state trip unit circuits H02H
• CPC Class Codes: H01H 83/04 with testing means for indicating the ability of the switch or relay to function properly
• CPC Class Codes: H02H 3/044 Checking correct functioning of protective arrangements, e.g. by simulating a fault for differential current circuit breakers H02H3/335
• CPC Class Codes: H02H 3/334 with means to produce an artificial unbalance for other protection or monitoring reasons or remote control H02H3/338 takes precedence

Abstract

The present invention provides a circuit interrupting device which can test the conditions of the components in the circuit interrupting device (i.e., the end-of-life test) through the depression of a test button. The circuit interrupting device also possesses reverse wiring protection, including the ability to cutoff power on the user accessible plugs of the face plate when the device is reverse wired or miswired. The circuit interrupting device contains a test button, a reset button, and a series of circuits (including, but not limited to, a main control circuit, an end-of-life detection circuit, and a reset/trip circuit). A depression of the test button generates a simulated fault, which is detected by the main control circuit. When the components in the main control circuit work properly, a control signal is generated by the main control circuit and transmitted to the end-of-life detection circuit to activate the reset/trip circuit and generated an indication signal. After the indication signal is displayed, the reset button is able to be depressed, which sends a signal to the end-of-life detection circuit, which in turn forwards the signal to the reset/trip circuit to reestablish the electrical continuity of the circuit interrupting device.

Claims

1. A circuit interrupting device comprising:

a test button;

a series of circuits comprising;

a main control circuit;

an end-of-life detection circuit; and

a reset/trip circuit; and

a reset button;

wherein when said circuit interrupting device is properly wired with power on and at a tripped state, a depression of said test button generates a simulated fault which is detected by said main control circuit;

wherein when components in said main control circuit work properly, a control signal is generated by said main control circuit and transmitted to said end-of-life detection circuit to activate said reset/trip circuit and generated an indication signal;

whereby after said indication signal is displayed, said reset button is able to be depressed to reestablish an electrical continuity of said circuit interrupting device; and

wherein when said components in said series of circuits do not work properly, said depression of said test button does not allow said fault signal to be generated and passed through said series of circuit which results in no production of said indication signal;

whereby said reset button is not able to be depressed and no electrical continuity is reestablished.

2. The circuit interrupting device according claim 1, wherein said main control circuit comprises a differential transformer and a leakage current detection chip (IC1);

and wherein said main control circuit is capable of detecting a fault.

3. The circuit interrupting device according to claim 1, wherein said end-of-life detection circuit comprises an end-of-life detection chip (IC2).

4. The circuit interrupting device according to claim 1, wherein said reset/trip circuit comprises a silicon controlled rectifier (SCR), and a solenoid coil with an iron core inside said solenoid coil.

5. The circuit interrupting device according to claim 1, wherein said indication signal is a sound.

6. The circuit interrupting device according to claim 1, wherein a metal piece is located underneath said test button, and a conductive pin is situated below said metal piece;

wherein said conductive pin is embedded in a conductive spring, which is adapted to electrically connected to one of a pair of power input terminals; and

wherein said metal piece is adapted to electrically connected to another one of said pair of power input terminals.

7. The circuit interrupting device according to claim 6, wherein when said test button is depressed, said metal piece is in contact with said conductive pin, which generates said simulated fault when said circuit interrupting device is properly wired.

8. The circuit interrupting device according to claim 7, wherein said simulated fault is generated through the use of a resistor, which is located at an electrical path between said conductive spring and said one of said pair of input terminals.

9. The circuit interrupting device according to claim 1, wherein when said circuit interrupting device is not at said tripped state, said depression of said test button mechanically breaks said electrical continuity of said circuit interrupting device.

10. The circuit interrupting device according to claim 2, wherein said IC1 is an RV4145 chip.

11. The circuit interrupting device according to claim 3, wherein said end of life detection circuit further comprises a flexible switch (K3);

wherein said K3 has a first conductive piece and a second conductive piece;

wherein said first conductive piece of said K3 is adapted to be coupled to said reset button and said second conductive piece of said K3 is adapted to be connected to a printed circuit board.

12. The circuit interrupting device according to claim 11, wherein said first conductive piece of said K3 is adapted to electrically connect to a power input source;

and wherein said second conductive piece of said K3 is adapted to electrically connected to a first input end of said IC2.

13. The circuit interrupting device according to claim 12, wherein said end of life detection circuit further comprises a triode or transistor (Q1) which is at an electrical path between an output end of said IC2 and said SCR.

14. The circuit interrupting device according to claim 13, wherein said IC2 comprises a first simulation switch (K1) and a second simulation switch (K2);

wherein said K1 and said K2 are operatively connected to said first input end of said IC2, whereby when said K3 is closed, said K1 and K2 are closed to allow a reset signal to be transmitted to said Q1.

15. The circuit interrupting device according to claim 14, wherein said IC2 further comprises a plurality of inverters and a NAND gate.

16. The circuit interrupting device according to claim 15, wherein said IC2 further comprises a second input end which is adapted to connect to said main control circuit and to receive said control signal;

wherein said second input end is operatively connected to said plurality of inverters and said NAND gate to control open/close of said K1 and/or said K2;

whereby when said control signal is received, said open/close of said K1 and/or said K2 outputs said control signal to said reset/trip circuit to activate said reset/trip circuit and generate said indication signal.

17. The circuit interrupting device according to claim 16, wherein said IC2 further comprises a time delay circuit capable of configuring a time frame to control said open/close of said K1 and/or said K2.

18. The circuit interrupting device according to claim 16, wherein said IC2 further comprises a third input end which receives a common collector voltage (Vcc) from a power input source;

wherein Vcc is generated after an alternating current (AC) from said power input source passes through a diode bridge (D1-D4) to be converted to a direct current (DC), and further passes through a resistor, a diode, and a capacity to be converted to said Vcc.

19. The circuit interrupting device according to claim 1, wherein said circuit interrupting device is a ground fault circuit interrupter, an arc fault circuit interrupter, an immersion detection circuit interrupter, an appliance leakage circuit interrupter, or a circuit breaker.

20. The circuit interrupting device according to claim 1, wherein said ground fault circuit interrupter comprises:

a housing;

a tripping device positioned in a base of said housing;

a printed circuit board positioned in said base of said housing;

said printed circuit board comprising;

a first pair of flexible metal pieces having a first end and a second end;

wherein said first pair of flexible metal pieces is operationally connected to power source input terminals;

said first end of each of said first pair of flexible metal pieces passing through a differential transformer being operationally connected to a hot input line or a neutral input line;

said second end of each of said first pair of flexible metal pieces having a movable contact;

a second pair of flexible metal pieces having a first end and a second end;

wherein said first end of each of said second pair of flexible metal pieces is operationally connected to a hot power output terminal or a neutral power output terminal;

said second end of each of said second pair of flexible metal pieces having a movable contact point;

a pair of output conductors positioned in an insulated middle support;

wherein each of said output conductors contains a pair of fixed contacts; and

wherein said movable contact of each of said first pair of flexible metal pieces and said movable contact of each of said second pair of flexible metal pieces are capable of connecting/disconnecting to each of said fixed contacts on said pair of output conductors.

21. A method for testing a circuit interrupting device according to claim 1, comprising:

when said circuit interrupting device is powered and at said tripped state, depressing said test button on said circuit interrupting device;

if said indicating signal is displayed, depressing said reset button to reset said circuit interrupting device;

whereby said display of said indication signal indicates that components of said circuit interrupting device work properly.

22. The method of claim 21, wherein if said circuit interrupting device is not at said tripped state, forcibly depressing said test button to mechanically trip said circuit interrupting device.

23. The method according to claim 21, wherein said indicating signal is a sound.

24. The method according to claim 21, wherein if said indicating signal is not displayed, replacing said circuit interrupting device with a new one.

25. The method according to claim 21, wherein said circuit interrupting device is a ground fault circuit interrupter.

26. An end-of-life detection chip (IC2) in an end-of-life detection circuit of a circuit interrupting device comprising:

a plurality of pins;

a first simulation switch (K1) and a second simulation switch (K2);

a plurality of inverters; and

a NAND gate;

wherein said plurality of pins comprise a first pin receiving a control signal from a main control circuit when said main control circuit detects a fault and components of said main control circuit works properly;

a second pin receiving a reset signal when a reset button is depressed; and

a third pin outputting said control signal and/or said reset signal to a reset/trip circuit;

wherein said first pin is operatively connected to said plurality of inverters and said NAND gate to control open/close of said K1 and/or said K2;

whereby when said control signal is received by said first pin, said open/close of said K1 and/or said K2 outputs said control signal via said third pin to said reset/trip circuit to activate said reset/trip circuit and generate an indication signal;

wherein said K1 and said K2 are further operatively connected to said second pin;

whereby when said reset signal is received by said second pin, said K1 and said K2 are closed, which allows said reset signal to be output via said third pin to said reset/trip circuit to reestablish an electrical continuity of said circuit interrupting device.

27. The IC2 according to claim 26, wherein said control signal is sent from an output end of a leakage current detection chip (IC1) in said main control circuit to said first pin of said IC2.

28. The IC2 according to claim 26, wherein said second pin of said IC2 is electrically connected to a flexible switch (K3) in said end-of-life detection circuit;

wherein said K3 has a first conductive piece and a second conductive piece;

wherein said first conductive piece of said K3 is adapted to be coupled to said reset button and said second conductive piece of said K3 is adapted to be connected to a printed circuit board;

wherein said first conductive piece of said K3 is adapted to electrically connect to a power input source; and

wherein said second conductive piece of said K3 is adapted to electrically connected to said second pin of said IC2.

29. The IC2 according to claim 26, wherein said third pin of said IC2 is electrically connected to a first end of a triode/transistor (Q1);

wherein a second end of said Q1 is adapted to be electrically connected to said reset/trip circuit;

whereby when said IC2 receives said control signal from said first pin or said reset signal from said second pin, said control signal or said reset signal is output via said third pin to said Q1, and to said reset/trip circuit.