Nonvolatile semiconductor memory

• US 7,539,056 B2
• Filed: 08/30/2007
• Issued: 05/26/2009
• Est. Priority Date: 02/01/2007
• Status: Expired due to Fees

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Sato, Mitsuru, Katsumata, Ryota, Kito, Masaru, Aochi, Hideaki, Kidoh, Masaru, Tanaka, Hiroyasu
• Primary Examiner(s): Dinh; Son
• Assistant Examiner(s): Nguyen; Hien N
• Application Number:
  US11/896,261
• Publication Number:
  US 20080186771A1
• Time in Patent Office: 635 Days
• Field of Search: 365/185.17, 365/185.11, 365/185.18, 365/185.27, 365/185.28, 365/185.14
• US Class Current: 365/185.18
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/24 Bit-line control circuits
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H10B 41/10 characterised by the top-view layout
• CPC Class Codes: H10B 41/35 with a cell select transistor, e.g. NAND
• CPC Class Codes: H10B 41/40 characterised by the peripheral circuit region
• CPC Class Codes: H10B 41/41 of a memory region comprising a cell select transistor, e.g. NAND

Abstract

In a NAND type flash memory, control electrodes of first select transistors in a plurality memory cell units extending along a data line is integrated to constitute a first select signal line while control electrodes of second select transistor are integrated to constitute a second select signal line. The second select signal line is displaced from the first select signal line by a half pitch.

Claims

1. A nonvolatile semiconductor memory comprising:

a data line;

a first memory cell unit including not only a first memory string in which a plurality of memory cells with charge accumulating regions are electrically connected in series but also first and second select transistors connected to said data line from one end of said first memory string;

a second memory cell unit including not only a second memory string structured similarly to said first memory string but also third and fourth select transistors connected to said data line from one end of said second memory string, said second memory cell unit being adjacent to said first memory cell unit;

a third memory cell unit including not only a third memory string structured similarly to said first memory string but also fifth and sixth select transistors connected to said data line from one end of said third memory string, said third memory cell unit being adjacent to said second memory cell unit;

a first select signal line electrically connected to a control electrode of said first select transistor of said first memory cell unit and to a control electrode of said third select transistor of said second memory cell unit; and

a second select signal line electrically connected to a control electrode of said fourth select transistor of said second memory cell unit and to a control electrode of said sixth select transistor of said third memory cell unit.

2. The nonvolatile semiconductor memory according to claim 1, wherein each of said first to third memory strings is constituted by a plurality of said memory cells stacked on a substrate.

3. The nonvolatile semiconductor memory according to claim 2, wherein said first, third and fifth select transistors are stuck on a first layer of said first to third memory strings, and said second, fourth and sixth select transistors are stuck on a second layer on said first layer.

4. The nonvolatile semiconductor memory according to claim 3, wherein the said data lines are placed on said second layers.

5. The nonvolatile semiconductor memory according to claim 4, wherein said first select signal line is placed in the said first layer and has a width extending across said first select transistor and said third select transistor, and said second select signal line is placed in the said second layer and has a width extending across said fourth select transistor and said sixth select transistor.

6. The nonvolatile semiconductor memory according to claim 5, wherein said second select signal line is displaced by a half pitch from a wiring pitch of said second select signal line.

7. The nonvolatile semiconductor memory according to claim 5, wherein said first and second select transistors are insulated gate field effect transistors.

8. The nonvolatile semiconductor memory according to claim 7, wherein each of said first and second select transistors includes said control electrode placed on said memory cells;

a gate insulator film placed on an inner wall of a through-hole longitudinally extending through said control electrode;

a channel forming region embedded in said inner wall of said through-hole via said gate insulator film; and

a pair of main electrode regions placed at opposite ends of said channel forming region.

9. The nonvolatile semiconductor memory according to claim 7, wherein each memory cell of said first to third memory strings includes a control gate electrode, a charge accumulating region placed on an inner wall of said through-hole extending through said control gate electrode, a channel forming region embedded in said inner wall of said through-hole via said charge accumulating region.

10. The nonvolatile semiconductor memory according to claim 8, wherein said first and second select transistors are made of gate electrode materials, and said data lines are made of conductive films having low resistances compared to resistance of said control electrode.

11. The nonvolatile semiconductor memory according to claim 1, further comprising:

a memory cell array in which said first to third memory cell units are arranged and which has first to fourth sides;

a select gate driver placed along said first side of said memory cell array, and including a first driver unit activating said first select signal line and a second driver unit activating said second signal line;

a select gate decoder controlling operations of said select gate driver;

a word line driver placed along said second side opposite to said first side of said memory cell array, and activating word lines connected to said memory cell arrays of said first to third memory strings;

a word line decoder controlling operations of said word line driver;

a column decoder including elements separately placed along said third and fourth sides of said memory cell array, and selecting said data lines, the third side being present between said first and second sides, and the fourth side being opposite to said third side; and

a sense amplifier including elements separately placed along said third and fourth sides, and connected to said data lines.

12. The nonvolatile semiconductor memory according to claim 5, further comprising:

a memory cell array in which said first to third memory cell units are arranged and which has first to fourth sides;

a select gate driver placed along said first side of said memory cell array, and including a first driver unit activating said first select signal line and a second driver unit activating said second signal line;

a select gate decoder controlling operations of said select gate driver;

a word line driver placed along said second side opposite to said first side of said memory cell array, and activating said word lines connected to said memory cell arrays of said first to third memory strings;

a word line decoder controlling operations of said word line driver;

a column decoder including elements separately placed along said third and fourth sides of said memory cell array, and selecting said data lines, said third side being present between said first and second sides, and said fourth side being opposite to said third side; and

a sense amplifier including elements separately placed along said third and fourth sides, and connected to said data lines.

13. The nonvolatile semiconductor memory according to claim 1 is a NAND type flash memory.

14. A nonvolatile semiconductor memory comprising:

a first memory cell unit including a first memory string to which a plurality of memory cells having charge accumulating regions and placed on a surface of a substrate are electrically connected in series;

a first enhancement type select transistor electrically connected in series to one end of said first memory string; and

a second depression type select transistor electrically connected in series to said first select transistor;

a second memory cell unit including a second memory string structured similarly to said first memory string;

a third depression type select transistor electrically connected in series to one end of said second memory string;

a fourth enhancement type select transistor electrically connected in series to said third select transistor, said second memory cell unit being adjacent to said first memory cell unit;

a first select signal line connected to said first and third select transistors;

a second select signal line connected to said second and fourth select transistors; and

a data line extending across said first and second memory cell units, and electrically connected to said second select transistor of said first memory cell unit and said fourth select transistor of said second memory cell unit.

15. The nonvolatile semiconductor memory according to claim 14, wherein said first and second memory cell units are electrically connected in series to one of said data line, and extend along said data line.

16. The nonvolatile semiconductor memory according to claim 14, wherein each of said first to fourth select transistors includes said control electrode;

a gate insulator film placed on an inner wall of a through-hole longitudinally extending through said control electrode;

a channel forming region embedded in said inner wall of said through-hole; and

a pair of main electrode regions placed at opposite ends of said channel forming region.

17. The nonvolatile semiconductor memory according to claim 14, wherein each of memory cells in said first and second memory cell strings includes a control gate electrode;

a charge accumulating region placed on an inner wall of a through-hole longitudinally extending through said control gate electrode; and

a channel forming region, embedded in said inner wall of said through-hole via said charge accumulating region, a source and a drain.

18. The nonvolatile semiconductor memory according to claim 14, further comprising:

a memory cell array in which said first and second memory cell units are arranged and which has first to fourth sides;

a first select gate driver placed along said first side of said memory cell array, and activating said first select transistor of said first memory cell unit and said third select transistor of said second memory cell unit;

a first select gate decoder controlling operations of said first gate driver;

a second select gate driver placed along said second side opposite to said first side of said memory cell array, and activating said second select transistor of said first memory cell unit and said fourth select transistor of said second memory cell unit;

a second select gate decoder controlling operations of said second select gate driver;

a word line driver placed along said third side between said first and second sides of said memory cell array, and activating word lines connected to said memory cell arrays of said first and second memory strings;

a word line decoder controlling operations of said word line driver;

a column decoder placed along said fourth side opposite to said third side of said memory cell array, and selecting said data lines; and

a sense amplifier placed along said fourth side, and connected to said data line.

19. The nonvolatile semiconductor memory according to claim 14 is a NAND type flash memory.

20. A nonvolatile semiconductor memory comprising:

a data line;

a first memory cell unit including not only a memory string to which a plurality of memory cells having charge accumulating regions are electrically connected in series but also a first enhancement type select transistor, a second depression type select transistor, a third enhancement type select transistor, and a fourth depression type selector, all of which are electrically connected in series to one end of said first memory string;

a second memory cell unit configured similarly to said first memory unit, electrically connected in parallel to said data lines, and being adjacent to said first memory cell unit along said data lines;

a third memory cell unit including a memory string which is structured similarly to said memory string of said first memory cell unit, and includes a fifth depression type select transistor, a sixth enhancement type select transistor, a seventh depression type select transistor, and an eighth enhancement type select transistors, said third memory cell unit being adjacent to said second memory cell unit along said data line and electrically connected in parallel to said data line;

a fourth memory cell unit being adjacent to said third and second memory cell units, extending along said data line, electrically connected to said data line, and structured similarly to said third memory cell unit;

a first select signal line electrically connected not only to control electrodes of said first select transistors of said first and second memory cell units but also to control electrodes of said fifth select transistors of said third and fourth memory cell units;

a second select signal line electrically connected not only to control electrodes of said second select transistors of said first and second memory cell units but also to control electrodes of said sixth select transistors of said third and fourth memory cell units, said second select signal line extending along said data line with a half pitch displaced from said first select signal line;

a third select signal line electrically connected not only to control electrodes of said third select transistors of said first and second memory cell units but also to control electrodes of said seventh select transistors of said third and fourth memory cell units, said second select signal line extending along said data line with a pitch same as that of said first select signal line; and

a fourth select signal line electrically connected not only to control electrodes of said fourth select transistors of said first and second memory cell units but also to control electrodes of said eighth select transistors of said third and fourth memory cell units, said fourth select signal line being arranged with a pitch same as that of said second select signal line.