Method and system for low-power integrating decision feedback equalizer with fast switched-capacitor feed forward path

• US 7,539,243 B1
• Filed: 03/31/2008
• Issued: 05/26/2009
• Est. Priority Date: 03/31/2008
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Toifl, Thomas H., Menolfi, Christian I., Schmatz, Martin Leo
• Primary Examiner(s): Payne; David C
• Assistant Examiner(s): Wong; Linda
• Application Number:
  US12/060,140
• Time in Patent Office: 421 Days
• Field of Search: 375229-236, 327101-108, 327/111, 327165-169, 327311-316, 327321-323, 327552-555
• US Class Current: 375/229
• CPC Class Codes: H04L 2025/0349 as a feedback filter
• CPC Class Codes: H04L 25/03057 with a recursive structure H04L25/03031 takes precedence

Abstract

A method and system for decision feedback equalization for digital transmission systems is provided. Low-power integrating decision feedback equalization with fast switched-capacitor paths are used, for suppressing intersymbol interference (ISI) due to past data symbols. The decision feedback equalization involves performing current-integrating decision feedback equalization at low-power employing a fast capacitively coupled feed-forward path at the output of a current-integrating buffer and inducing voltage changes by charge redistribution via coupled switching capacitors, and performing a voltage digital-to-analog conversation to determine a feedback coefficient as a coupling voltage. Then switches are reset to a pre-charge coupling voltage in the buffers to eliminate residual ISI caused by signal history, thereby achieving current integrating buffering with switched-capacitor feedback during the integration, and the capacitive switches are triggered by previous symbols.

Claims

1. A method of decision feedback equalization for digital transmission systems, using decisions on previously transmitted data symbols to suppress intersymbol interference (ISI) due to past data symbols, comprising:

performing current-integrating decision feedback equalization at low-power, employing a fast capacitively coupled feed-forward path, including coupled switching capacitors, at the output of a current integrating buffer providing integration nodes, and inducing voltage changes by charge redistribution via the coupled switching capacitors;

employing a digital-to-analog converter (DAC) via switches at coupling nodes to the coupled switching capacitors, for performing a voltage digital-to-analog conversion to determine a feedback coefficient as a coupling voltage;

performing pre-charging of the coupled switching capacitors to a defined analog voltage value by resetting the switches to a pre-charge the coupling voltage to inject a defined charge on the integration nodes, and

providing a well-controlled voltage drop at the integration nodes proportional to a feedback coefficient by grounding one of the coupling nodes via one of the switches in the buffers to eliminate thereby eliminating residual ISI caused by signal history, thereby and achieving current integrating buffering with switched-capacitor feedback during the integration and

wherein said resetting involves triggering the capacitive switches by previous symbols.