Wireless LAN apparatus and semiconductor device

• US 7,539,477 B2
• Filed: 11/09/2005
• Issued: 05/26/2009
• Est. Priority Date: 11/11/2004
• Status: Active Grant

• Current Assignee: Ricoh Company Limited
• Original Assignee: Ricoh Company Limited
• Inventors: Kubota, Syuji, Ueno, Mayuko, Kimura, Sadahiro
• Primary Examiner(s): Trinh; Sonny
• Application Number:
  US11/269,849
• Publication Number:
  US 20060121952A1
• Time in Patent Office: 1,294 Days
• Field of Search: 455/574, 455/343.1, 455/343.2, 455/343.4, 455/572, 455/127.1, 455/127.5, 370/311, 370/338, 370/345
• US Class Current: 455/343.1
• CPC Class Codes: H04W 52/0283 with sequential power up or power down of successive circuit blocks, e.g. switching on the local oscillator before RF or mixer stages
• CPC Class Codes: Y02D 30/70 in wireless communication networks

Abstract

A wireless LAN apparatus is disclosed that includes a module group section that is connected to an upper level CPU of an upper level apparatus, an RF processing part that is connected to the module group section, a power reduction instruction dispatching section for dispatching a power reduction instruction, a power reduction instruction receiving section for receiving the power reduction instruction dispatched from the power reduction instruction section, and a power reduction sequence controlling section for controlling power of the module group section in a predetermined order in accordance with the power reduction instruction dispatched by the power reduction instruction dispatching section.

Claims

1. A wireless LAN apparatus comprising:

a module group section that is connected to an upper level CPU of an upper level apparatus;

an RF processing part that is connected to the module group section;

a power reduction instruction dispatching section for dispatching a power reduction instruction;

a power reduction instruction receiving section for receiving the power reduction instruction dispatched from the power reduction instruction section;

a power reduction sequence controlling section for controlling power of the module group section in a predetermined order in accordance with the power reduction instruction dispatched by the power reduction instruction dispatching section; and

wherein the module group section includes a BB processing part for processing base band signals and the power reduction instruction includes the BB processing part as part of the predetermined order.

2. The wireless LAN apparatus as claimed in claim 1, wherein the module group section is included in an IC chip having

a MAC processing part for conducting media access control,

the BB processing part for processing base band signals, and

an inside CPU for processing a portion of the workload of the upper level CPU.

3. The wireless LAN apparatus as claimed in claim 2, wherein the upper level CPU is configured to function as the power reduction instruction dispatching section, wherein the inside CPU is configured to function as the power reduction instruction receiving section and the power reduction sequence controlling section.

4. The wireless LAN apparatus as claimed in claim 3, wherein the module group section further includes

a first oscillator for transmitting a first oscillator clock signal to the inside CPU, and

a second oscillator for transmitting a second oscillator clock signal to the RF processing part.

5. The wireless LAN apparatus as claimed in claim 1, wherein the module group section includes a MAC processing part for conducting media access control.

6. The wireless LAN apparatus as claimed in claim 5, wherein the upper level CPU is configured to function as the power reduction instruction dispatching section, the power reduction instruction receiving section and the power reduction sequence controlling section.

7. The wireless LAN apparatus as claimed in claim 6, wherein the module group section further includes an oscillator for transmitting a clock signal to the RF processing part.

8. A wireless LAN apparatus comprising:

a module group section that is connected to an upper level CPU of an upper level apparatus;

an RF processing part that is connected to the module group section;

a power reduction instruction dispatching section for dispatching a power reduction instruction;

a power reduction instruction receiving section for receiving the power reduction instruction dispatched from the power reduction instruction section;

a power reduction seciuence controlling section for controlling power of the module group section in a predetermined order in accordance with the power reduction instruction dispatched by the power reduction instruction dispatching section;

wherein the module group section is included in an IC chin having a MAC processing part for conducting media access control, a BB processing part for processing base band signals, an inside CPU for processing a portion of the workload of the upper level CPU, a first oscillator for transmitting a first oscillator clock signal to the inside CPU, and a second oscillator for transmitting a second oscillator clock signal to the RF processing part;

wherein the upper level CPU is configured to function as the power reduction instruction dispatching section, wherein the inside CPU is configured to function as the power reduction instruction receiving section and the power reduction sequence controlling section; and

wherein the power reduction sequence controlling section reduces the power of the MAC processing part, the BB processing part, the inside CPU, the first oscillator, and the second oscillator in an order of the MAC processing part, the BB processing part, the second oscillator, the first oscillator, and the inside CPU.

9. The wireless LAN apparatus as claimed in claim 8, wherein the power reduction sequence controlling section restores the power of the MAC processing part, the BB processing part, the inside CPU, the first oscillator, and the second oscillator in an order of the first oscillator, the inside CPU, the second oscillator, the BB processing part, and the MAC processing part.

10. A wireless LAN apparatus comprising:

a module group section that is connected to an upper level CPU of an upper level apparatus;

an RF processing part that is connected to the module group section;

a power reduction instruction dispatching section for dispatching a power reduction instruction;

a power reduction instruction receiving section for receiving the power reduction instruction dispatched from the power reduction instruction section;

a power reduction secinence controlling section for controlling power of the module group section in a predetermined order in accordance with the power reduction instruction dispatched by the power reduction instruction dispatching section;

wherein the module group section includes a MAC processing part for conducting media access control, a BB processing part for processing base band signals, and an oscillator for transmitting a clocks signal to the RF processing part;

wherein the upper level CPU is configured to function as the power reduction instruction dispatching section, the power reduction instruction receiving section and the power reduction seciuence controlling section; and

wherein the power reduction sequence controlling section reduces the power of the MAC processing part, the BB processing part, and the oscillator in an order of the MAC processing part, the BB processing part, and the oscillator.

11. The wireless LAN apparatus as claimed in claim 10, wherein the power reduction sequence controlling section restores the power of the MAC processing part, the BB processing part, and the oscillator in an order of the oscillator, the BB processing part, and the MAC processing part.

12. A semiconductor device used for a wireless LAN apparatus including a power reduction function, the semiconductor device comprising:

a power reduction instruction receiving section for receiving a power reduction instruction dispatched from the wireless LAN apparatus;

a power reduction sequence controlling section for controlling power of a module group section included in the wireless LAN apparatus in a predetermined order in accordance with the power reduction instruction dispatched by the power reduction instruction dispatching section; and

wherein the module group section includes a BB processing part for processing base band signals and the power reduction instruction includes the BB processing part as part of the predetermined order.

13. The semiconductor device as claimed in claim 12, further comprising:

a MAC processing part for conducting media access control, and

an inside CPU for processing a portion of the workload of an upper level CPU of an upper level apparatus connected to the wireless LAN apparatus.