Microcomputer logic development
First Claim
1. A logic development system using an external microcomputer which replaces a built-in microcomputer incorporated in an existing electronic control unit, comprising:
- a mother board including an application block and a first communication block;
a core board including one or more devices which simulate, by software, peripheral devices of the built-in microcomputer so as to execute an input or output process, the core board further including a computing block and a second communication block;
a peripheral component interconnect (PCI) bus coupling said mother board and said core board;
an interface board including a port assignment conversion board, a plurality of standard circuits, and a plurality of facility boards which are associated with hardware of said electronic control unit, said standard circuits and facility boards being selectable by said port assignment conversion board, and said port assignment conversion board being coupled to said core board via a harness; and
a bus controller in said computing block interposed between said first communication block in said mother board and each of said one or more devices,an internal memory in said computing block coupled to said bus controller over a first internal bus, wherein,said first communication block included in said mother board and said bus controller are coupled to each other over said PCI bus, and said bus controller and each of said one or more devices are coupled to each other over a second internal bus,said first communication block and each of said one or more devices transfer data to or from each other according to two transfer techniques,wherein a first one of the two transfer techniques transfers a first portion of the data by way of said PCI bus, bus controller, and the second internal bus without using said internal memory, the first one of the two transfer techniques being invoked for acquiring input information on the mother board during a first action of an application, anda second one of the two transfer techniques transfers a second portion of the data via said internal memory, wherein the second portion of the data from one of said one or more devices is stored in said internal memory via said first internal bus and said bus controller, and the second portion of the data stored in said internal memory is transmitted to said first communication block via said bus controller concurrently, wherein the second transfer technique is carried out before a second action of the application responsive to an interrupt request from the core board to the mother board.
1 Assignment
0 Petitions
Accused Products
Abstract
Provided is a logic development system that can ensure the capability of a CPU required for preceding logic, guarantee reliable communication of input/output information, and improve the throughput of the CPU. A logic development system for a built-in microcomputer employed in an electronic control unit (ECU) comprises: a motherboard that accommodates an application facility and a communication facility; a core board that accommodates quasi microcomputer peripheral devices, a, computing facility, and a communication facility and that is connected to the motherboard over a PCI bus; and an interface board that includes circuits equivalent to the hardware of the ECU and that is connected to the core board. The communication facility on the motherboard and each of the quasi microcomputer peripheral devices on the core board transfer data directly to or from each other over the PCI bus linking them.
17 Citations
23 Claims
-
1. A logic development system using an external microcomputer which replaces a built-in microcomputer incorporated in an existing electronic control unit, comprising:
-
a mother board including an application block and a first communication block; a core board including one or more devices which simulate, by software, peripheral devices of the built-in microcomputer so as to execute an input or output process, the core board further including a computing block and a second communication block; a peripheral component interconnect (PCI) bus coupling said mother board and said core board; an interface board including a port assignment conversion board, a plurality of standard circuits, and a plurality of facility boards which are associated with hardware of said electronic control unit, said standard circuits and facility boards being selectable by said port assignment conversion board, and said port assignment conversion board being coupled to said core board via a harness; and a bus controller in said computing block interposed between said first communication block in said mother board and each of said one or more devices, an internal memory in said computing block coupled to said bus controller over a first internal bus, wherein, said first communication block included in said mother board and said bus controller are coupled to each other over said PCI bus, and said bus controller and each of said one or more devices are coupled to each other over a second internal bus, said first communication block and each of said one or more devices transfer data to or from each other according to two transfer techniques, wherein a first one of the two transfer techniques transfers a first portion of the data by way of said PCI bus, bus controller, and the second internal bus without using said internal memory, the first one of the two transfer techniques being invoked for acquiring input information on the mother board during a first action of an application, and a second one of the two transfer techniques transfers a second portion of the data via said internal memory, wherein the second portion of the data from one of said one or more devices is stored in said internal memory via said first internal bus and said bus controller, and the second portion of the data stored in said internal memory is transmitted to said first communication block via said bus controller concurrently, wherein the second transfer technique is carried out before a second action of the application responsive to an interrupt request from the core board to the mother board. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21)
-
-
22. A logic development method for a microcomputer including a mother board having an application block and a first communication block, a core board having one or more devices which simulate, by software, peripheral devices of the built-in microcomputer so as to execute an input or output process, the core board further including a computing block and a second communication block, an interface board having a port assignment conversion board, a plurality of standard circuits, and a plurality of facility boards which are associated with hardware of an electronic control unit, said standard circuits and facility boards being selectable by said port assignment conversion board, and said port assignment conversion board being coupled to said core board via a harness, a peripheral component interconnect (PCI) bus over which said mother board and said core board are coupled to each other, a bus controller in said computing block interposed between said first communication block in said mother board and each of said peripheral devices, an internal memory in said computing block coupled to said bus controller over a first internal bus, said microcomputer logic development method comprising:
-
issuing an interrupt request from said core board to said mother board over a one-channel interrupt signal line contained in said PCI bus; accepting the interrupt request when said interrupt signal line is activated via said core board; inactivating said interrupt signal line after the interrupt request is accepted; transferring data between said first communication block and each of the peripheral devices according to two transfer techniques, wherein, a first one of the two transfer techniques transfers a first portion of the data by way of said PCI bus, bus controller, and the second internal bus without using said internal memory, the first one of the two transfer techniques being invoked for acquiring input information on the mother board during a first action of an application, and a second one of the two transfer techniques transfers a second portion of the data via said internal memory, wherein the second portion of the data from one of the peripheral devices is stored in said internal memory via said first internal bus and said bus controller, and the second portion of the data stored in said internal memory is transmitted to said first communication block via said bus controller concurrently, wherein the second transfer technique is carried out before a second action of the application responsive to the interrupt request from the core board to the mother board. - View Dependent Claims (23)
-
Specification