Multi-port memory device providing protection signal

• US 7,539,825 B2
• Filed: 02/01/2006
• Issued: 05/26/2009
• Est. Priority Date: 10/25/2001
• Status: Expired due to Fees

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Suh, Woon-Sik, Lee, Yun-Tae, Sohn, Han-Gu, Kim, Sei-Jin
• Primary Examiner(s): Portka; Gary J
• Application Number:
  US11/345,054
• Publication Number:
  US 20060161338A1
• Time in Patent Office: 1,210 Days
• Field of Search: 711/149, 711/151, 711/153
• US Class Current: 711/149
• CPC Class Codes: G06F 13/1647 with interleaved bank access
• CPC Class Codes: G11C 11/4087 Address decoders, e.g. bit - or word line decoders; Multiple line decoders
• CPC Class Codes: G11C 11/4096 Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
• CPC Class Codes: G11C 7/1012 Data reordering during input/output, e.g. crossbars, layers of multiplexers, shifting or rotating
• CPC Class Codes: G11C 7/1051 Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
• CPC Class Codes: G11C 7/1063 Control signal output circuits, e.g. status or busy flags, feedback command signals
• CPC Class Codes: G11C 7/1075 for multiport memories each having random access ports and serial ports, e.g. video RAM
• CPC Class Codes: G11C 8/12 Group selection circuits, e.g. for memory block selection, chip selection, array selection

Abstract

A memory system includes a first external device, a second external device, and a multi-port memory device connected to the first and second external devices. The multi-port memory system includes: a first port and a second port connected to the first and second external devices, respectively, a first bank group having at least one memory bank, the first bank group configured to be accessed by the first external device through the first data port; a second bank group having at least one memory bank, the second bank group configured to be accessed by the second external device through the second data port; a third bank group having at least one memory bank, wherein the third bank group is configured to be selectively accessed by the first external device through the first data port or the second external device through the second data port. The multi-port memory system may prevent data collisions which occur when two ports simultaneously attempt to access the same memory bank.

Claims

1. A multi-port memory device comprising:

a first port and a second port connected to a first and second external device, respectively;

a first bank group having at least one memory bank, the first bank group configured to be accessed by the first external device through the first port;

a second bank group having at least one memory bank, the second bank group configured to be accessed by the second external device through the second port;

a third bank group having at least one memory bank, wherein the third bank group is configured to be selectively accessed by the first external device through the first port and the second external device through the second port; and

a selection circuit that receives requests from the first port and the second port to access a same bank of the third bank group and grants access to the requested bank in the third bank group to one of the first and second external devices and denies access to the other device according to a priority value stored in the multi-port memory device,

wherein the priority value indicates which of the first and second ports has a higher priority, and

wherein the requests comprise a first bank selection signal and a second bank selection signal and the selection circuit transfers a first protection signal to the device that is granted access and a second protection signal to the device that is denied access according to the priority.

2. The multi-port memory device of claim 1, wherein the selection circuit includes:

a priority decision unit to receive the first bank selection signal and the second bank selection signal to select the same bank in the third bank group, and to generate a first acceptance signal and a second acceptance signal according to the priority; and

a protection signal generator for generating the first protection signal and the second protection signal in response to the first and second acceptance signals.

3. The multi-port memory device of claim 1, wherein the stored priority is implemented as a hardwired configuration.

4. The multi-port memory device of claim 1, further comprising a register for storing the priority.

5. The multi-port memory device of claim 4, wherein the register stores allocation information indicating (1) which of the banks in the first to third bank groups are allocated only to the first port, (2) which of the banks in the first to third bank groups are allocated only to the second port, and (3) which of the first to third bank groups are shared by both the first and second ports.

6. The multi-port memory device of claim 1, wherein the first external device is a modem and the second external device is an AP (access point).

7. The multi-port memory device of claim 1, wherein the multi-port memory device is an SDRAM (synchronous dynamic random access memory).

8. A memory system comprising:

a first processor;

a second processor; and

a multi-port memory device connected to the first and second processors,

wherein the multi-port memory device includes;

a first port and a second port connected to the first and second processors, respectively;

a first bank group having at least one memory bank, the first bank group configured to be accessed by the first processor through the first port;

a second bank group having at least one memory bank, the second bank group configured to be accessed by the second processor through the second port;

a third bank group having at least one memory bank, wherein the third bank group is configured to be selectively accessed by the first processor through the first port and the second processor through the second port; and

a selection circuit that receives requests from the first port and the second port to access a same bank of the third bank group and grants access to the requested bank in the third bank group to one of the first and second processors and denies access to the other processor according to a priority value stored in the multi-port memory device,

wherein the priority value indicates which of the first and second ports has a higher priority, and

wherein the requests comprise a first bank selection signal and a second bank selection signal and the selection circuit transfers a first protection signal to the processor that is granted access and a second protection signal to the processor that is denied access according to the priority.

9. The memory system of claim 8, wherein the selection circuit includes:

a priority decision unit to receive the first bank selection signal and a second bank selection signal to select the same bank in the third bank group, and to generate a first acceptance signal and a second acceptance signal according to the priority; and

a protection signal generator for generating the first protection signal and the second protection signal in response to the first and second acceptance signals.

10. The memory system of claim 9, wherein the stored priority is implemented as a hardwired configuration.

11. The memory system of claim 8, further comprising a register for storing the priority.

12. The memory system of claim 11, wherein the register stores allocation information indicating (1) which of the banks in the first to third bank groups are allocated only to the first port, (2) which of the banks in the first to third bank groups are allocated only to the second port, and (3) which of the first to third bank groups are shared by both the first and second ports.

13. The memory system of claim 8, wherein the first processor is a modem and the second processor is an AP (access point).

14. The memory system of claim 8, wherein the multi-port memory device is an SDRAM (synchronous dynamic random access memory).