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High speed hardware implementation of modified Reed-Solomon decoder

  • US 7,539,927 B2
  • Filed: 04/14/2005
  • Issued: 05/26/2009
  • Est. Priority Date: 04/14/2005
  • Status: Active Grant
First Claim
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1. A decoder suitable for use in a digital communications system utilizing an RS(n′

  • , k′

    ) code modified from an RS(n, k) code, wherein the decoder receives n′

    -symbol vectors each including k′

    message symbols and r′

    =n′



    k′

    parity symbols and decodes the n′

    -symbol vectors to correct errors therein, wherein n, k, n′

    , and k′

    are integers, and k′

    <

    n′

    <

    n, k′

    <

    k <

    n, and wherein the decoder stores one erasure locator polynomial σ

    0(x), the decoder comprising;

    a syndrome calculator for receiving the n′

    -symbol vectors and for calculating syndromes of each n′

    -symbol vector, wherein the i-th syndrome Si of one n′

    -symbol vector R′

    , (rn′



    1
    , rn′



    2
    , . . . , r0), is Si=Rs

    i+1) for i=0, 1, . . . , n−

    k−

    1, wherein Rs(x)=rn′



    1
    xn′



    1
    +rn′



    2
    xn′



    2
    + . . . +r0;

    an index adjustment circuit for generating an adjusted error/erasure locator polynomial {tilde over (σ

    )}(x) and an adjusted error/erasure evaluator polynomial {tilde over (ω

    )}(x) based on the syndromes calculated by the syndrome calculator;

    a memory device for storing the one erasure locator polynomial σ

    0(x) and a look-up table; and

    means for finding the locations and values of the errors in each n′

    -symbol vector based on the adjusted error/erasure locator polynomial {tilde over (σ

    )}(x) and the adjusted error/erasure evaluator polynomial {tilde over (ω

    )}(x), using the look-up table.

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